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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Tvrtko Ursulin <tursulin@ursulin.net>
Cc: Intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/5] drm/i915: More assorted dev_priv cleanups
Date: Fri, 4 Nov 2016 17:32:30 +0200	[thread overview]
Message-ID: <20161104153230.GP4617@intel.com> (raw)
In-Reply-To: <1478270568-7902-3-git-send-email-tvrtko.ursulin@linux.intel.com>

On Fri, Nov 04, 2016 at 02:42:45PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> A small selection of macros which can only accept dev_priv from
> now on and a resulting trickle of fixups.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h       | 27 ++++++++++++---------------
>  drivers/gpu/drm/i915/i915_gpu_error.c |  2 +-
>  drivers/gpu/drm/i915/i915_irq.c       |  6 +++---
>  drivers/gpu/drm/i915/intel_crt.c      |  8 ++++----
>  drivers/gpu/drm/i915/intel_display.c  |  4 ++--
>  drivers/gpu/drm/i915/intel_dp.c       |  2 +-
>  drivers/gpu/drm/i915/intel_hotplug.c  |  2 +-
>  drivers/gpu/drm/i915/intel_psr.c      |  2 +-
>  8 files changed, 25 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 45a30f730216..6060e41d25e5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2901,28 +2901,25 @@ struct drm_i915_cmd_table {
>  #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
>  					 !(IS_I915G(dev_priv) || \
>  					 IS_I915GM(dev_priv)))
> -#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
> -#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)
> -
> -#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
> -#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
> -#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
> +#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
> +#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
>  
> +#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
> +#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
> +#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
>  #define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
> -
> -#define HAS_DP_MST(dev)	(INTEL_INFO(dev)->has_dp_mst)
> -
> +#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
>  #define HAS_DDI(dev_priv)	((dev_priv)->info.has_ddi)
> -#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
> -#define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)
> -#define HAS_RC6(dev)		(INTEL_INFO(dev)->has_rc6)
> -#define HAS_RC6p(dev)		(INTEL_INFO(dev)->has_rc6p)
> -
> -#define HAS_CSR(dev)	(INTEL_INFO(dev)->has_csr)
> +#define HAS_PSR(dev_priv)	((dev_priv)->info.has_psr)
> +#define HAS_RC6(dev_priv)	((dev_priv)->info.has_rc6)
> +#define HAS_RC6p(dev_priv)	((dev_priv)->info.has_rc6p)
> +#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
>  
>  #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
>  #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
>  
> +#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)

What's confusing me is this reordering of these macros. Was there a
particular reason for doing that?

Outside that it all looks pretty reasonable. Could got a bit further
with passing around dev_priv in some cases, but I guess we can leave
that to future work.


One random idea that did pop into my head was this:

static inline const struct ... *
intel_info(struct drm_i915_private *dev_priv)
{
	return &dev_priv->info;
}
#define HAS_WHATEVER(dev_priv) (intel_info(dev_priv)->whatever)

for some extra type safety. Any thoughts?

> +
>  /*
>   * For now, anything with a GuC requires uCode loading, and then supports
>   * command submission once loaded. But these are logically independent
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index d430b9441e6b..35b13f178b61 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -573,7 +573,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
>  		   pdev->subsystem_device);
>  	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
>  
> -	if (HAS_CSR(dev)) {
> +	if (HAS_CSR(dev_priv)) {
>  		struct intel_csr *csr = &dev_priv->csr;
>  
>  		err_printf(m, "DMC loaded: %s\n",
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 6d7505b5c5e7..285ee1e4352a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3678,7 +3678,7 @@ static void i915_irq_preinstall(struct drm_device * dev)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	int pipe;
>  
> -	if (I915_HAS_HOTPLUG(dev)) {
> +	if (I915_HAS_HOTPLUG(dev_priv)) {
>  		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
>  		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
>  	}
> @@ -3712,7 +3712,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
>  		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
>  		I915_USER_INTERRUPT;
>  
> -	if (I915_HAS_HOTPLUG(dev)) {
> +	if (I915_HAS_HOTPLUG(dev_priv)) {
>  		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
>  		POSTING_READ(PORT_HOTPLUG_EN);
>  
> @@ -3880,7 +3880,7 @@ static void i915_irq_uninstall(struct drm_device * dev)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	int pipe;
>  
> -	if (I915_HAS_HOTPLUG(dev)) {
> +	if (I915_HAS_HOTPLUG(dev_priv)) {
>  		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
>  		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 30eb95b54dcf..fed61958ffd4 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -693,7 +693,7 @@ intel_crt_detect(struct drm_connector *connector, bool force)
>  	power_domain = intel_display_port_power_domain(intel_encoder);
>  	intel_display_power_get(dev_priv, power_domain);
>  
> -	if (I915_HAS_HOTPLUG(dev)) {
> +	if (I915_HAS_HOTPLUG(dev_priv)) {
>  		/* We can not rely on the HPD pin always being correctly wired
>  		 * up, for example many KVM do not pass it through, and so
>  		 * only trust an assertion that the monitor is connected.
> @@ -715,7 +715,7 @@ intel_crt_detect(struct drm_connector *connector, bool force)
>  	 * broken monitor (without edid) to work behind a broken kvm (that fails
>  	 * to have the right resistors for HP detection) needs to fix this up.
>  	 * For now just bail out. */
> -	if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) {
> +	if (I915_HAS_HOTPLUG(dev_priv) && !i915.load_detect_test) {
>  		status = connector_status_disconnected;
>  		goto out;
>  	}
> @@ -915,7 +915,7 @@ void intel_crt_init(struct drm_device *dev)
>  		crt->base.disable = intel_disable_crt;
>  	}
>  	crt->base.enable = intel_enable_crt;
> -	if (I915_HAS_HOTPLUG(dev) &&
> +	if (I915_HAS_HOTPLUG(dev_priv) &&
>  	    !dmi_check_system(intel_spurious_crt_detect))
>  		crt->base.hpd_pin = HPD_CRT;
>  	if (HAS_DDI(dev_priv)) {
> @@ -932,7 +932,7 @@ void intel_crt_init(struct drm_device *dev)
>  
>  	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
>  
> -	if (!I915_HAS_HOTPLUG(dev))
> +	if (!I915_HAS_HOTPLUG(dev_priv))
>  		intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
>  
>  	/*
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 97589102442c..bf8099ed0b20 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8438,7 +8438,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
>  		}
>  	}
>  
> -	if (HAS_PIPE_CXSR(dev)) {
> +	if (HAS_PIPE_CXSR(dev_priv)) {
>  		if (intel_crtc->lowfreq_avail) {
>  			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
>  			pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
> @@ -15620,7 +15620,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>  	} else if (IS_GEN2(dev_priv))
>  		intel_dvo_init(dev);
>  
> -	if (SUPPORTS_TV(dev))
> +	if (SUPPORTS_TV(dev_priv))
>  		intel_tv_init(dev);
>  
>  	intel_psr_init(dev);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index d4e9cf3ad26e..4c9981ccfc23 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5742,7 +5742,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  	}
>  
>  	/* init MST on ports that can support it */
> -	if (HAS_DP_MST(dev) && !is_edp(intel_dp) &&
> +	if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
>  	    (port == PORT_B || port == PORT_C || port == PORT_D))
>  		intel_dp_mst_encoder_init(intel_dig_port,
>  					  intel_connector->base.base.id);
> diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
> index 334d47b5811a..3d546c019de0 100644
> --- a/drivers/gpu/drm/i915/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/intel_hotplug.c
> @@ -501,7 +501,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
>  		if (intel_connector->mst_port)
>  			continue;
>  
> -		if (!connector->polled && I915_HAS_HOTPLUG(dev) &&
> +		if (!connector->polled && I915_HAS_HOTPLUG(dev_priv) &&
>  		    intel_connector->encoder->hpd_pin > HPD_NONE) {
>  			connector->polled = enabled ?
>  				DRM_CONNECTOR_POLL_CONNECT |
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 271a3e29ff23..41e6e920d9d7 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -427,7 +427,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
>  
> -	if (!HAS_PSR(dev)) {
> +	if (!HAS_PSR(dev_priv)) {
>  		DRM_DEBUG_KMS("PSR not supported on this platform\n");
>  		return;
>  	}
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2016-11-04 15:32 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-04 14:42 [PATCH 0/5] dev_priv cleanup continuation Tvrtko Ursulin
2016-11-04 14:42 ` [PATCH 1/5] drm/i915: Assorted dev_priv cleanups Tvrtko Ursulin
2016-11-09 10:37   ` David Weinehall
2016-11-04 14:42 ` [PATCH 2/5] drm/i915: More assorted " Tvrtko Ursulin
2016-11-04 15:32   ` Ville Syrjälä [this message]
2016-11-04 16:03     ` Tvrtko Ursulin
2016-11-04 16:29       ` Ville Syrjälä
2016-11-07  9:29         ` [PATCH v2 " Tvrtko Ursulin
2016-11-09 10:38           ` David Weinehall
2016-11-04 14:42 ` [PATCH 3/5] drm/i915: Further " Tvrtko Ursulin
2016-11-09 10:38   ` David Weinehall
2016-11-04 14:42 ` [PATCH 4/5] drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from the gen use Tvrtko Ursulin
2016-11-09 10:38   ` David Weinehall
2016-11-09 11:30     ` [PATCH v2 " Tvrtko Ursulin
2016-11-09 11:42       ` David Weinehall
2016-11-04 14:42 ` [PATCH 5/5] drm/i915: Convert i915_drv.c to INTEL_GEN Tvrtko Ursulin
2016-11-09 10:39   ` David Weinehall
2016-11-04 15:23 ` ✗ Fi.CI.BAT: failure for dev_priv cleanup continuation Patchwork
2016-11-07 10:45 ` ✓ Fi.CI.BAT: success for dev_priv cleanup continuation (rev2) Patchwork
2016-11-09 12:45 ` ✓ Fi.CI.BAT: success for dev_priv cleanup continuation (rev3) Patchwork
2016-11-10  9:42   ` Tvrtko Ursulin
2016-11-10 12:00     ` Joonas Lahtinen
2016-11-11 15:01     ` Tvrtko Ursulin

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