From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v4 4/8] drm/i915/gen9: WM memory bandwidth related workaround
Date: Fri, 4 Nov 2016 19:22:31 +0200 [thread overview]
Message-ID: <20161104172231.GS4617@intel.com> (raw)
In-Reply-To: <1478279344.2535.151.camel@intel.com>
On Fri, Nov 04, 2016 at 03:09:04PM -0200, Paulo Zanoni wrote:
> Em Qui, 2016-10-13 às 16:28 +0530, Kumar, Mahesh escreveu:
> > This patch implemnets Workariunds related to display arbitrated
> > memory
> > bandwidth. These WA are applicabe for all gen-9 based platforms.
> >
> > Changes since v1:
> > - Rebase on top of Paulo's patch series
> > Changes since v2:
> > - Rebase/rework after addressing Paulo's comments in previous patch
>
> A lot of this code has changed since then, so this will need a
> significant rebase. In the meantime, I added skl_needs_memory_bw_wa()
> and we're now applying the WA by default: we just won't apply the WA
> when we're pretty sure we don't need to. This helps avoiding underruns
> by default.
>
> See more below.
>
>
> >
> > Signed-off-by: "Kumar, Mahesh" <mahesh1.kumar@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 9 +++
> > drivers/gpu/drm/i915/intel_drv.h | 11 +++
> > drivers/gpu/drm/i915/intel_pm.c | 146
> > +++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 166 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index adbd9aa..c169360 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1092,6 +1092,13 @@ enum intel_sbi_destination {
> > SBI_MPHY,
> > };
> >
> > +/* SKL+ Watermark arbitrated display bandwidth Workarounds */
> > +enum watermark_memory_wa {
> > + WATERMARK_WA_NONE,
> > + WATERMARK_WA_X_TILED,
> > + WATERMARK_WA_Y_TILED,
> > +};
> > +
> > #define QUIRK_PIPEA_FORCE (1<<0)
> > #define QUIRK_LVDS_SSC_DISABLE (1<<1)
> > #define QUIRK_INVERT_BRIGHTNESS (1<<2)
> > @@ -1644,6 +1651,8 @@ struct skl_ddb_allocation {
> >
> > struct skl_wm_values {
> > unsigned dirty_pipes;
> > + /* any WaterMark memory workaround Required */
>
> We can remove this comment since it doesn't say anything the variable
> name doesn't.
>
> > + enum watermark_memory_wa mem_wa;
>
> Now that we have a proper variable in the state struct, it probably
> makes sense to just kill skl_needs_memory_bw_wa() and read this
> variable when we need to.
>
>
> > struct skl_ddb_allocation ddb;
> > uint32_t wm_linetime[I915_MAX_PIPES];
> > uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index f48e79a..2c1897b 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1813,6 +1813,17 @@ intel_atomic_get_crtc_state(struct
> > drm_atomic_state *state,
> > return to_intel_crtc_state(crtc_state);
> > }
> >
> > +static inline struct intel_crtc_state *
> > +intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
> > + struct intel_crtc *crtc)
> > +{
> > + struct drm_crtc_state *crtc_state;
> > +
> > + crtc_state = drm_atomic_get_existing_crtc_state(state,
> > &crtc->base);
> > +
> > + return to_intel_crtc_state(crtc_state);
>
> I really don't like the idea of calling to_intel_crtc_state() on a
> potentially NULL pointer so the caller of this function will also check
> for NULL. Even though it works today, I still think it's unsafe
> practice. Please check crtc_state for NULL directly and then return
> NULL.
I want to make this safe by making it a compile error if offsetof(base) != 0.
https://lists.freedesktop.org/archives/intel-gfx/2016-October/108175.html
But I think we want to go further than that patch by adding a bit more
type safety to things. I did play around with this stuff a bit more,
and I have something sitting on a branch, but I didn't quite figure out
what I want to do about const vs. non const yet.
>
> Also, I think this function should be extracted to its own commit, and
> we'd probably be able to find some callers in the existing i915 code.
I have, on some branch again, _intel_ versions of the for_each_foo_in_state()
macros as well. I think those are going to allow a lot of ugly casting
stuff to disappear. But I think I'll hold off until Maarten's new
iterators go in before I try to send those out.
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2016-11-04 17:22 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-13 10:58 [PATCH v4 0/8] New DDB Algo and WM fixes Kumar, Mahesh
2016-10-13 10:58 ` [PATCH v4 1/8] drm/i915/skl+: use linetime latency instead of ddb size Kumar, Mahesh
2016-10-31 18:03 ` Paulo Zanoni
2016-11-09 14:58 ` Mahesh Kumar
2016-11-09 17:02 ` Paulo Zanoni
2016-10-13 10:58 ` [PATCH v4 2/8] drm/i915/skl: New ddb allocation algorithm Kumar, Mahesh
2016-11-04 19:25 ` Paulo Zanoni
2016-10-13 10:58 ` [PATCH v4 3/8] drm/i915: Decode system memory bandwidth Kumar, Mahesh
2016-11-03 19:06 ` Paulo Zanoni
2016-11-16 11:48 ` Mahesh Kumar
2016-10-13 10:58 ` [PATCH v4 4/8] drm/i915/gen9: WM memory bandwidth related workaround Kumar, Mahesh
2016-11-04 17:09 ` Paulo Zanoni
2016-11-04 17:22 ` Ville Syrjälä [this message]
2016-11-10 5:54 ` Mahesh Kumar
2016-11-16 12:36 ` Paulo Zanoni
2016-10-13 10:58 ` [PATCH v4 5/8] drm/i915/skl+: reset y_plane ddb structure also during calculation Kumar, Mahesh
2016-11-04 17:39 ` Paulo Zanoni
2016-10-13 10:58 ` [PATCH v4 6/8] drm/i915/skl: Add variables to check x_tile and y_tile Kumar, Mahesh
2016-11-04 17:45 ` Paulo Zanoni
2016-10-13 10:58 ` [PATCH v4 7/8] drm/i915/skl+: change WM calc to fixed point 16.16 Kumar, Mahesh
2016-11-04 19:03 ` Paulo Zanoni
2016-10-13 10:58 ` [PATCH v4 8/8] drm/i915/bxt: Enable IPC support Kumar, Mahesh
2016-10-13 11:19 ` Maarten Lankhorst
2016-10-13 13:01 ` Mahesh Kumar
2016-10-13 15:36 ` Daniel Vetter
2016-11-04 19:20 ` Paulo Zanoni
2016-10-13 13:50 ` ✗ Fi.CI.BAT: warning for New DDB Algo and WM fixes (rev4) Patchwork
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