From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36339) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c4avH-00056Q-Pt for qemu-devel@nongnu.org; Wed, 09 Nov 2016 17:00:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c4avC-00072H-V6 for qemu-devel@nongnu.org; Wed, 09 Nov 2016 17:00:47 -0500 Received: from mx1.redhat.com ([209.132.183.28]:42900) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c4avC-00071u-O5 for qemu-devel@nongnu.org; Wed, 09 Nov 2016 17:00:42 -0500 Date: Thu, 10 Nov 2016 00:00:39 +0200 From: "Michael S. Tsirkin" Message-ID: <20161109235951-mutt-send-email-mst@kernel.org> References: <1478603064-32562-1-git-send-email-bd.aviv@gmail.com> <1478603064-32562-2-git-send-email-bd.aviv@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v6 1/3] IOMMU: add option to enable VTD_CAP_CM to vIOMMU capility exposoed to guest List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jason Wang Cc: "Aviv B.D" , qemu-devel@nongnu.org, Jan Kiszka , Alex Williamson , Peter Xu On Wed, Nov 09, 2016 at 03:28:02PM +0800, Jason Wang wrote: >=20 >=20 > On 2016=E5=B9=B411=E6=9C=8808=E6=97=A5 19:04, Aviv B.D wrote: > > From: "Aviv Ben-David" > >=20 > > This capability asks the guest to invalidate cache before each map op= eration. > > We can use this invalidation to trap map operations in the hypervisor= . >=20 > Hi: >=20 > Like I've asked twice in the past, I want to know why don't you cache > translation faults as what spec required (especially this is a guest vi= sible > behavior)? >=20 > Btw, please cc me on posting future versions. >=20 > Thanks Caching isn't guest visible. Spec just says you *can* cache, not that you must. > >=20 > > Signed-off-by: Aviv Ben-David > > --- > > hw/i386/intel_iommu.c | 5 +++++ > > hw/i386/intel_iommu_internal.h | 1 + > > include/hw/i386/intel_iommu.h | 2 ++ > > 3 files changed, 8 insertions(+) > >=20 > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > > index 1655a65..834887f 100644 > > --- a/hw/i386/intel_iommu.c > > +++ b/hw/i386/intel_iommu.c > > @@ -2017,6 +2017,7 @@ static Property vtd_properties[] =3D { > > DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState, intr_eim, > > ON_OFF_AUTO_AUTO), > > DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, fal= se), > > + DEFINE_PROP_BOOL("cache-mode", IntelIOMMUState, cache_mode_enabl= ed, FALSE), > > DEFINE_PROP_END_OF_LIST(), > > }; > > @@ -2391,6 +2392,10 @@ static void vtd_init(IntelIOMMUState *s) > > assert(s->intr_eim !=3D ON_OFF_AUTO_AUTO); > > } > > + if (s->cache_mode_enabled) { > > + s->cap |=3D VTD_CAP_CM; > > + } > > + > > vtd_reset_context_cache(s); > > vtd_reset_iotlb(s); > > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_int= ernal.h > > index 0829a50..35d9f3a 100644 > > --- a/hw/i386/intel_iommu_internal.h > > +++ b/hw/i386/intel_iommu_internal.h > > @@ -201,6 +201,7 @@ > > #define VTD_CAP_MAMV (VTD_MAMV << 48) > > #define VTD_CAP_PSI (1ULL << 39) > > #define VTD_CAP_SLLPS ((1ULL << 34) | (1ULL << 35)) > > +#define VTD_CAP_CM (1ULL << 7) > > /* Supported Adjusted Guest Address Widths */ > > #define VTD_CAP_SAGAW_SHIFT 8 > > diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_io= mmu.h > > index 1989c1e..42d293f 100644 > > --- a/include/hw/i386/intel_iommu.h > > +++ b/include/hw/i386/intel_iommu.h > > @@ -258,6 +258,8 @@ struct IntelIOMMUState { > > uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read return= s 0) */ > > uint32_t version; > > + bool cache_mode_enabled; /* RO - is cap CM enabled? */ > > + > > dma_addr_t root; /* Current root table pointer *= / > > bool root_extended; /* Type of root table (extended= or not) */ > > bool dmar_enabled; /* Set if DMA remapping is enab= led */