diff for duplicates of <20161118184437.GD19884@dell.home> diff --git a/a/1.txt b/N1/1.txt index fe9b6c0..84c907d 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -7,7 +7,7 @@ Do you have a preference? > fifth generation SoCs depends on bits in both the System Control Unit > and the LPC Host Controller. > -> Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org> +> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > --- > Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt | 17 +++++++++++++++++ @@ -39,7 +39,7 @@ Why not just use a single tab, then you don't have to linewrap? > +Example: > + -> +lpchc: lpchc@1e7890a0 { +> +lpchc: lpchc at 1e7890a0 { > + compatible = "aspeed,ast2500-lpchc", "syscon"; > + reg = <0x1e7890a0 0xc4>; > +}; @@ -47,9 +47,5 @@ Why not just use a single tab, then you don't have to linewrap? -- Lee Jones Linaro STMicroelectronics Landing Team Lead -Linaro.org │ Open source software for ARM SoCs +Linaro.org ? Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog --- -To unsubscribe from this list: send the line "unsubscribe devicetree" in -the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org -More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index fb2fec1..d8b5fc8 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,18 +1,9 @@ "ref\01478097481-14895-1-git-send-email-andrew@aj.id.au\0" "ref\01478097481-14895-4-git-send-email-andrew@aj.id.au\0" - "ref\01478097481-14895-4-git-send-email-andrew-zrmu5oMJ5Fs@public.gmane.org\0" - "From\0Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" - "Subject\0Re: [PATCH v2 3/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LPCHC)\0" + "From\0lee.jones@linaro.org (Lee Jones)\0" + "Subject\0[PATCH v2 3/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LPCHC)\0" "Date\0Fri, 18 Nov 2016 18:44:37 +0000\0" - "To\0Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>\0" - "Cc\0Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>" - Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org> - Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> - Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> - linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Arnd,\n" @@ -24,7 +15,7 @@ "> fifth generation SoCs depends on bits in both the System Control Unit\n" "> and the LPC Host Controller.\n" "> \n" - "> Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>\n" + "> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>\n" "> ---\n" "> Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt | 17 +++++++++++++++++\n" "\n" @@ -56,7 +47,7 @@ "\n" "> +Example:\n" "> +\n" - "> +lpchc: lpchc@1e7890a0 {\n" + "> +lpchc: lpchc at 1e7890a0 {\n" "> +\tcompatible = \"aspeed,ast2500-lpchc\", \"syscon\";\n" "> +\treg = <0x1e7890a0 0xc4>;\n" "> +};\n" @@ -64,11 +55,7 @@ "-- \n" "Lee Jones\n" "Linaro STMicroelectronics Landing Team Lead\n" - "Linaro.org \342\224\202 Open source software for ARM SoCs\n" - "Follow Linaro: Facebook | Twitter | Blog\n" - "--\n" - "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" - "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" - More majordomo info at http://vger.kernel.org/majordomo-info.html + "Linaro.org ? Open source software for ARM SoCs\n" + Follow Linaro: Facebook | Twitter | Blog -6031db7ba116c762fd39ade1d2f1b61d720dc5d4fdae8e4d1b3a3e5f4b6d8601 +4b03cef5cd3785012963055d551d5b03759dbaeeed6ecdcc2af28c87dc078775
diff --git a/a/1.txt b/N2/1.txt index fe9b6c0..6a50bd8 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -7,7 +7,7 @@ Do you have a preference? > fifth generation SoCs depends on bits in both the System Control Unit > and the LPC Host Controller. > -> Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org> +> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > --- > Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt | 17 +++++++++++++++++ @@ -49,7 +49,3 @@ Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog --- -To unsubscribe from this list: send the line "unsubscribe devicetree" in -the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org -More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N2/content_digest index fb2fec1..21387d4 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,18 +1,17 @@ "ref\01478097481-14895-1-git-send-email-andrew@aj.id.au\0" "ref\01478097481-14895-4-git-send-email-andrew@aj.id.au\0" - "ref\01478097481-14895-4-git-send-email-andrew-zrmu5oMJ5Fs@public.gmane.org\0" - "From\0Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" + "From\0Lee Jones <lee.jones@linaro.org>\0" "Subject\0Re: [PATCH v2 3/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LPCHC)\0" "Date\0Fri, 18 Nov 2016 18:44:37 +0000\0" - "To\0Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>\0" - "Cc\0Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>" - Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org> - Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> - Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> - linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "To\0Andrew Jeffery <andrew@aj.id.au>\0" + "Cc\0Linus Walleij <linus.walleij@linaro.org>" + Joel Stanley <joel@jms.id.au> + Mark Rutland <mark.rutland@arm.com> + Rob Herring <robh+dt@kernel.org> + linux-gpio@vger.kernel.org + linux-arm-kernel@lists.infradead.org + linux-kernel@vger.kernel.org + " devicetree@vger.kernel.org\0" "\00:1\0" "b\0" "Arnd,\n" @@ -24,7 +23,7 @@ "> fifth generation SoCs depends on bits in both the System Control Unit\n" "> and the LPC Host Controller.\n" "> \n" - "> Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>\n" + "> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>\n" "> ---\n" "> Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt | 17 +++++++++++++++++\n" "\n" @@ -65,10 +64,6 @@ "Lee Jones\n" "Linaro STMicroelectronics Landing Team Lead\n" "Linaro.org \342\224\202 Open source software for ARM SoCs\n" - "Follow Linaro: Facebook | Twitter | Blog\n" - "--\n" - "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" - "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" - More majordomo info at http://vger.kernel.org/majordomo-info.html + Follow Linaro: Facebook | Twitter | Blog -6031db7ba116c762fd39ade1d2f1b61d720dc5d4fdae8e4d1b3a3e5f4b6d8601 +74d4be3729f74141e895766477d1da66e5cbf19bb13b767b89e34c9abc3f43be
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