From: Mahesh Kumar <mahesh1.kumar@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: paulo.r.zanoni@intel.com, maarten.lankhorst@intel.com
Subject: [PATCH v6 3/8] drm/i915/kbl: IPC workaround for kabylake
Date: Thu, 24 Nov 2016 09:31:30 +0530 [thread overview]
Message-ID: <20161124040135.5517-4-mahesh1.kumar@intel.com> (raw)
In-Reply-To: <20161124040135.5517-1-mahesh1.kumar@intel.com>
IPC (Isoch Priority Control) may cause underflows.
KBL WA: When IPC is enabled, watermark latency values must be increased
by 4us across all levels. This brings level 0 up to 6us.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7090a7c..33d22cc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3603,6 +3603,10 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
fb->modifier == I915_FORMAT_MOD_Yf_TILED;
x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
+ /* IPC WA for kabylake */
+ if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
+ latency += 4;
+
if (apply_memory_bw_wa && x_tiled)
latency += 15;
--
2.10.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2016-11-24 4:00 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-24 4:01 [PATCH v5 0/8] GEN-9 Arbitrated Bandwidth WM WA's & IPC Mahesh Kumar
2016-11-24 4:01 ` [PATCH v6 1/8] drm/i915/skl: Add variables to check x_tile and y_tile Mahesh Kumar
2016-11-24 4:01 ` [PATCH v6 2/8] drm/i915/bxt: IPC WA for Broxton Mahesh Kumar
2016-11-24 12:51 ` Lankhorst, Maarten
2016-11-28 13:07 ` Mahesh Kumar
2016-12-01 11:02 ` Lankhorst, Maarten
2016-11-24 4:01 ` Mahesh Kumar [this message]
2016-11-24 4:01 ` [PATCH v6 4/8] drm/i915/bxt: Enable IPC support Mahesh Kumar
2016-11-24 4:01 ` [PATCH v6 5/8] drm/i915/skl+: change WM calc to fixed point 16.16 Mahesh Kumar
2016-11-24 4:01 ` [PATCH v6 6/8] drm/i915: Add intel_atomic_get_existing_crtc_state function Mahesh Kumar
2016-11-24 4:01 ` [PATCH v6 7/8] drm/i915: Decode system memory bandwidth Mahesh Kumar
2016-11-24 10:10 ` kbuild test robot
2016-11-24 4:01 ` [PATCH v6 8/8] drm/i915/gen9: WM memory bandwidth related workaround Mahesh Kumar
2016-11-24 12:51 ` Lankhorst, Maarten
2016-11-29 5:42 ` Mahesh Kumar
2016-11-29 9:46 ` Lankhorst, Maarten
2016-11-29 13:47 ` Mahesh Kumar
2016-11-29 15:10 ` Lankhorst, Maarten
2016-11-24 4:45 ` ✓ Fi.CI.BAT: success for GEN-9 Arbitrated Bandwidth WM WA's & IPC (rev2) Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20161124040135.5517-4-mahesh1.kumar@intel.com \
--to=mahesh1.kumar@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=maarten.lankhorst@intel.com \
--cc=paulo.r.zanoni@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.