From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eric Anholt Subject: [PATCH 3/6] drm/vc4: Add support for the VEC (Video Encoder) IP Date: Tue, 29 Nov 2016 10:41:59 -0800 Message-ID: <20161129184202.10640-4-eric@anholt.net> References: <20161129184202.10640-1-eric@anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from anholt.net (anholt.net [50.246.234.109]) by gabe.freedesktop.org (Postfix) with ESMTP id 797F36E50D for ; Tue, 29 Nov 2016 18:42:11 +0000 (UTC) In-Reply-To: <20161129184202.10640-1-eric@anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org List-Id: dri-devel@lists.freedesktop.org RnJvbTogQm9yaXMgQnJlemlsbG9uIDxib3Jpcy5icmV6aWxsb25AZnJlZS1lbGVjdHJvbnMuY29t PgoKVGhlIFZFQyBJUCBpcyBhIFRWIERBQywgcHJvdmlkaW5nIHN1cHBvcnQgZm9yIFBBTCBhbmQg TlRTQyBzdGFuZGFyZHMuCgpTaWduZWQtb2ZmLWJ5OiBCb3JpcyBCcmV6aWxsb24gPGJvcmlzLmJy ZXppbGxvbkBmcmVlLWVsZWN0cm9ucy5jb20+ClNpZ25lZC1vZmYtYnk6IEVyaWMgQW5ob2x0IDxl cmljQGFuaG9sdC5uZXQ+Ci0tLQogZHJpdmVycy9ncHUvZHJtL3ZjNC9NYWtlZmlsZSAgICAgIHwg ICAxICsKIGRyaXZlcnMvZ3B1L2RybS92YzQvdmM0X2RlYnVnZnMuYyB8ICAgMSArCiBkcml2ZXJz L2dwdS9kcm0vdmM0L3ZjNF9kcnYuYyAgICAgfCAgIDEgKwogZHJpdmVycy9ncHUvZHJtL3ZjNC92 YzRfZHJ2LmggICAgIHwgICA1ICsKIGRyaXZlcnMvZ3B1L2RybS92YzQvdmM0X3ZlYy5jICAgICB8 IDY1NyArKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKwogNSBmaWxlcyBjaGFu Z2VkLCA2NjUgaW5zZXJ0aW9ucygrKQogY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvZ3B1L2Ry bS92YzQvdmM0X3ZlYy5jCgpkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL3ZjNC9NYWtlZmls ZSBiL2RyaXZlcnMvZ3B1L2RybS92YzQvTWFrZWZpbGUKaW5kZXggZmI3N2RiNzU1ZTBhLi43NzU3 ZjY5YThhNzcgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS92YzQvTWFrZWZpbGUKKysrIGIv ZHJpdmVycy9ncHUvZHJtL3ZjNC9NYWtlZmlsZQpAQCAtMTEsNiArMTEsNyBAQCB2YzQteSA6PSBc CiAJdmM0X2ttcy5vIFwKIAl2YzRfZ2VtLm8gXAogCXZjNF9oZG1pLm8gXAorCXZjNF92ZWMubyBc CiAJdmM0X2h2cy5vIFwKIAl2YzRfaXJxLm8gXAogCXZjNF9wbGFuZS5vIFwKZGlmZiAtLWdpdCBh L2RyaXZlcnMvZ3B1L2RybS92YzQvdmM0X2RlYnVnZnMuYyBiL2RyaXZlcnMvZ3B1L2RybS92YzQv dmM0X2RlYnVnZnMuYwppbmRleCAyNDUxMTVkNDljNDYuLmNhZjgxN2JhYzg4NSAxMDA2NDQKLS0t IGEvZHJpdmVycy9ncHUvZHJtL3ZjNC92YzRfZGVidWdmcy5jCisrKyBiL2RyaXZlcnMvZ3B1L2Ry bS92YzQvdmM0X2RlYnVnZnMuYwpAQCAtMTksNiArMTksNyBAQCBzdGF0aWMgY29uc3Qgc3RydWN0 IGRybV9pbmZvX2xpc3QgdmM0X2RlYnVnZnNfbGlzdFtdID0gewogCXsiYm9fc3RhdHMiLCB2YzRf Ym9fc3RhdHNfZGVidWdmcywgMH0sCiAJeyJkcGlfcmVncyIsIHZjNF9kcGlfZGVidWdmc19yZWdz LCAwfSwKIAl7ImhkbWlfcmVncyIsIHZjNF9oZG1pX2RlYnVnZnNfcmVncywgMH0sCisJeyJ2ZWNf cmVncyIsIHZjNF92ZWNfZGVidWdmc19yZWdzLCAwfSwKIAl7Imh2c19yZWdzIiwgdmM0X2h2c19k ZWJ1Z2ZzX3JlZ3MsIDB9LAogCXsiY3J0YzBfcmVncyIsIHZjNF9jcnRjX2RlYnVnZnNfcmVncywg MCwgKHZvaWQgKikodWludHB0cl90KTB9LAogCXsiY3J0YzFfcmVncyIsIHZjNF9jcnRjX2RlYnVn ZnNfcmVncywgMCwgKHZvaWQgKikodWludHB0cl90KTF9LApkaWZmIC0tZ2l0IGEvZHJpdmVycy9n cHUvZHJtL3ZjNC92YzRfZHJ2LmMgYi9kcml2ZXJzL2dwdS9kcm0vdmM0L3ZjNF9kcnYuYwppbmRl eCA4NmFhYmY2ZDBmNzkuLmRmM2RhMjZhODQ5ZSAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJt L3ZjNC92YzRfZHJ2LmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL3ZjNC92YzRfZHJ2LmMKQEAgLTI5 NCw2ICsyOTQsNyBAQCBzdGF0aWMgY29uc3Qgc3RydWN0IGNvbXBvbmVudF9tYXN0ZXJfb3BzIHZj NF9kcm1fb3BzID0gewogCiBzdGF0aWMgc3RydWN0IHBsYXRmb3JtX2RyaXZlciAqY29uc3QgY29t cG9uZW50X2RyaXZlcnNbXSA9IHsKIAkmdmM0X2hkbWlfZHJpdmVyLAorCSZ2YzRfdmVjX2RyaXZl ciwKIAkmdmM0X2RwaV9kcml2ZXIsCiAJJnZjNF9odnNfZHJpdmVyLAogCSZ2YzRfY3J0Y19kcml2 ZXIsCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vdmM0L3ZjNF9kcnYuaCBiL2RyaXZlcnMv Z3B1L2RybS92YzQvdmM0X2Rydi5oCmluZGV4IGI2MDQ5Y2MyNTY3NS4uMTYyODIxNzk2YmYzIDEw MDY0NAotLS0gYS9kcml2ZXJzL2dwdS9kcm0vdmM0L3ZjNF9kcnYuaAorKysgYi9kcml2ZXJzL2dw dS9kcm0vdmM0L3ZjNF9kcnYuaApAQCAtMTcsNiArMTcsNyBAQCBzdHJ1Y3QgdmM0X2RldiB7CiAJ c3RydWN0IHZjNF9jcnRjICpjcnRjWzNdOwogCXN0cnVjdCB2YzRfdjNkICp2M2Q7CiAJc3RydWN0 IHZjNF9kcGkgKmRwaTsKKwlzdHJ1Y3QgdmM0X3ZlYyAqdmVjOwogCiAJc3RydWN0IGRybV9mYmRl dl9jbWEgKmZiZGV2OwogCkBAIC00ODYsNiArNDg3LDEwIEBAIGludCB2YzRfcXVldWVfc2Vxbm9f Y2Ioc3RydWN0IGRybV9kZXZpY2UgKmRldiwKIGV4dGVybiBzdHJ1Y3QgcGxhdGZvcm1fZHJpdmVy IHZjNF9oZG1pX2RyaXZlcjsKIGludCB2YzRfaGRtaV9kZWJ1Z2ZzX3JlZ3Moc3RydWN0IHNlcV9m aWxlICptLCB2b2lkICp1bnVzZWQpOwogCisvKiB2YzRfaGRtaS5jICovCitleHRlcm4gc3RydWN0 IHBsYXRmb3JtX2RyaXZlciB2YzRfdmVjX2RyaXZlcjsKK2ludCB2YzRfdmVjX2RlYnVnZnNfcmVn cyhzdHJ1Y3Qgc2VxX2ZpbGUgKm0sIHZvaWQgKnVudXNlZCk7CisKIC8qIHZjNF9pcnEuYyAqLwog aXJxcmV0dXJuX3QgdmM0X2lycShpbnQgaXJxLCB2b2lkICphcmcpOwogdm9pZCB2YzRfaXJxX3By ZWluc3RhbGwoc3RydWN0IGRybV9kZXZpY2UgKmRldik7CmRpZmYgLS1naXQgYS9kcml2ZXJzL2dw dS9kcm0vdmM0L3ZjNF92ZWMuYyBiL2RyaXZlcnMvZ3B1L2RybS92YzQvdmM0X3ZlYy5jCm5ldyBm aWxlIG1vZGUgMTAwNjQ0CmluZGV4IDAwMDAwMDAwMDAwMC4uMzJiYjhlZjk4NWZiCi0tLSAvZGV2 L251bGwKKysrIGIvZHJpdmVycy9ncHUvZHJtL3ZjNC92YzRfdmVjLmMKQEAgLTAsMCArMSw2NTcg QEAKKy8qCisgKiBDb3B5cmlnaHQgKEMpIDIwMTYgQnJvYWRjb20KKyAqCisgKiBUaGlzIHByb2dy YW0gaXMgZnJlZSBzb2Z0d2FyZTsgeW91IGNhbiByZWRpc3RyaWJ1dGUgaXQgYW5kL29yIG1vZGlm eSBpdAorICogdW5kZXIgdGhlIHRlcm1zIG9mIHRoZSBHTlUgR2VuZXJhbCBQdWJsaWMgTGljZW5z ZSB2ZXJzaW9uIDIgYXMgcHVibGlzaGVkIGJ5CisgKiB0aGUgRnJlZSBTb2Z0d2FyZSBGb3VuZGF0 aW9uLgorICoKKyAqIFRoaXMgcHJvZ3JhbSBpcyBkaXN0cmlidXRlZCBpbiB0aGUgaG9wZSB0aGF0 IGl0IHdpbGwgYmUgdXNlZnVsLCBidXQgV0lUSE9VVAorICogQU5ZIFdBUlJBTlRZOyB3aXRob3V0 IGV2ZW4gdGhlIGltcGxpZWQgd2FycmFudHkgb2YgTUVSQ0hBTlRBQklMSVRZIG9yCisgKiBGSVRO RVNTIEZPUiBBIFBBUlRJQ1VMQVIgUFVSUE9TRS4gIFNlZSB0aGUgR05VIEdlbmVyYWwgUHVibGlj IExpY2Vuc2UgZm9yCisgKiBtb3JlIGRldGFpbHMuCisgKgorICogWW91IHNob3VsZCBoYXZlIHJl Y2VpdmVkIGEgY29weSBvZiB0aGUgR05VIEdlbmVyYWwgUHVibGljIExpY2Vuc2UgYWxvbmcgd2l0 aAorICogdGhpcyBwcm9ncmFtLiAgSWYgbm90LCBzZWUgPGh0dHA6Ly93d3cuZ251Lm9yZy9saWNl bnNlcy8+LgorICovCisKKy8qKgorICogRE9DOiBWQzQgU0RUViBtb2R1bGUKKyAqLworCisjaW5j bHVkZSA8ZHJtL2RybV9hdG9taWNfaGVscGVyLmg+CisjaW5jbHVkZSA8ZHJtL2RybV9jcnRjX2hl bHBlci5oPgorI2luY2x1ZGUgPGRybS9kcm1fZWRpZC5oPgorI2luY2x1ZGUgPGRybS9kcm1fcGFu ZWwuaD4KKyNpbmNsdWRlIDxsaW51eC9jbGsuaD4KKyNpbmNsdWRlIDxsaW51eC9jb21wb25lbnQu aD4KKyNpbmNsdWRlIDxsaW51eC9vZl9ncmFwaC5oPgorI2luY2x1ZGUgPGxpbnV4L29mX3BsYXRm b3JtLmg+CisjaW5jbHVkZSA8bGludXgvcG1fcnVudGltZS5oPgorCisjaW5jbHVkZSAidmM0X2Ry di5oIgorI2luY2x1ZGUgInZjNF9yZWdzLmgiCisKKy8qIFdTRSBSZWdpc3RlcnMgKi8KKyNkZWZp bmUgVkVDX1dTRV9SRVNFVAkJCTB4YzAKKworI2RlZmluZSBWRUNfV1NFX0NPTlRST0wJCQkweGM0 CisjZGVmaW5lIFZFQ19XU0VfV1NTX0VOQUJMRQkJQklUKDcpCisKKyNkZWZpbmUgVkVDX1dTRV9X U1NfREFUQQkJMHhjOAorI2RlZmluZSBWRUNfV1NFX1ZQU19EQVRBMQkJMHhjYworI2RlZmluZSBW RUNfV1NFX1ZQU19DT05UUk9MCQkweGQwCisKKy8qIFZFQyBSZWdpc3RlcnMgKi8KKyNkZWZpbmUg VkVDX1JFVklECQkJMHgxMDAKKworI2RlZmluZSBWRUNfQ09ORklHMAkJCTB4MTA0CisjZGVmaW5l IFZFQ19DT05GSUcwX1lERUxfTUFTSwkJR0VOTUFTSygyOCwgMjYpCisjZGVmaW5lIFZFQ19DT05G SUcwX1lERUwoeCkJCSgoeCkgPDwgMjYpCisjZGVmaW5lIFZFQ19DT05GSUcwX0NERUxfTUFTSwkJ R0VOTUFTSygyNSwgMjQpCisjZGVmaW5lIFZFQ19DT05GSUcwX0NERUwoeCkJCSgoeCkgPDwgMjQp CisjZGVmaW5lIFZFQ19DT05GSUcwX1BCUFJfRklMCQlCSVQoMTgpCisjZGVmaW5lIFZFQ19DT05G SUcwX0NIUk9NQV9HQUlOX01BU0sJR0VOTUFTSygxNywgMTYpCisjZGVmaW5lIFZFQ19DT05GSUcw X0NIUk9NQV9HQUlOX1VOSVRZCSgwIDw8IDE2KQorI2RlZmluZSBWRUNfQ09ORklHMF9DSFJPTUFf R0FJTl8xXzMyCSgxIDw8IDE2KQorI2RlZmluZSBWRUNfQ09ORklHMF9DSFJPTUFfR0FJTl8xXzE2 CSgyIDw8IDE2KQorI2RlZmluZSBWRUNfQ09ORklHMF9DSFJPTUFfR0FJTl8xXzgJKDMgPDwgMTYp CisjZGVmaW5lIFZFQ19DT05GSUcwX0NCVVJTVF9HQUlOX01BU0sJR0VOTUFTSygxNCwgMTMpCisj ZGVmaW5lIFZFQ19DT05GSUcwX0NCVVJTVF9HQUlOX1VOSVRZCSgwIDw8IDEzKQorI2RlZmluZSBW RUNfQ09ORklHMF9DQlVSU1RfR0FJTl8xXzEyOAkoMSA8PCAxMykKKyNkZWZpbmUgVkVDX0NPTkZJ RzBfQ0JVUlNUX0dBSU5fMV82NAkoMiA8PCAxMykKKyNkZWZpbmUgVkVDX0NPTkZJRzBfQ0JVUlNU X0dBSU5fMV8zMgkoMyA8PCAxMykKKyNkZWZpbmUgVkVDX0NPTkZJRzBfQ0hSQlcxCQlCSVQoMTEp CisjZGVmaW5lIFZFQ19DT05GSUcwX0NIUkJXMAkJQklUKDEwKQorI2RlZmluZSBWRUNfQ09ORklH MF9TWU5DRElTCQlCSVQoOSkKKyNkZWZpbmUgVkVDX0NPTkZJRzBfQlVSRElTCQlCSVQoOCkKKyNk ZWZpbmUgVkVDX0NPTkZJRzBfQ0hSRElTCQlCSVQoNykKKyNkZWZpbmUgVkVDX0NPTkZJRzBfUERF TgkJQklUKDYpCisjZGVmaW5lIFZFQ19DT05GSUcwX1lDREVMQVkJCUJJVCg0KQorI2RlZmluZSBW RUNfQ09ORklHMF9SQU1QRU4JCUJJVCgyKQorI2RlZmluZSBWRUNfQ09ORklHMF9ZQ0RJUwkJQklU KDIpCisjZGVmaW5lIFZFQ19DT05GSUcwX1NURF9NQVNLCQlHRU5NQVNLKDEsIDApCisjZGVmaW5l IFZFQ19DT05GSUcwX05UU0NfU1RECQkwCisjZGVmaW5lIFZFQ19DT05GSUcwX1BBTF9CREdISV9T VEQJMQorI2RlZmluZSBWRUNfQ09ORklHMF9QQUxfTl9TVEQJCTMKKworI2RlZmluZSBWRUNfU0NI UEgJCQkweDEwOAorI2RlZmluZSBWRUNfU09GVF9SRVNFVAkJCTB4MTBjCisjZGVmaW5lIFZFQ19D TE1QMF9TVEFSVAkJCTB4MTQ0CisjZGVmaW5lIFZFQ19DTE1QMF9FTkQJCQkweDE0OAorI2RlZmlu ZSBWRUNfRlJFUTNfMgkJCTB4MTgwCisjZGVmaW5lIFZFQ19GUkVRMV8wCQkJMHgxODQKKworI2Rl ZmluZSBWRUNfQ09ORklHMQkJCTB4MTg4CisjZGVmaW5lIFZFQ19DT05GSUdfVkVDX1JFU1lOQ19P RkYJQklUKDE4KQorI2RlZmluZSBWRUNfQ09ORklHX1JHQjIxOQkJQklUKDE3KQorI2RlZmluZSBW RUNfQ09ORklHX0NCQVJfRU4JCUJJVCgxNikKKyNkZWZpbmUgVkVDX0NPTkZJR19UQ19PQkIJCUJJ VCgxNSkKKyNkZWZpbmUgVkVDX0NPTkZJRzFfT1VUUFVUX01PREVfTUFTSwlHRU5NQVNLKDEyLCAx MCkKKyNkZWZpbmUgVkVDX0NPTkZJRzFfQ19ZX0NWQlMJCSgwIDw8IDEwKQorI2RlZmluZSBWRUNf Q09ORklHMV9DVkJTX1lfQwkJKDEgPDwgMTApCisjZGVmaW5lIFZFQ19DT05GSUcxX1BSX1lfUEIJ CSgyIDw8IDEwKQorI2RlZmluZSBWRUNfQ09ORklHMV9SR0IJCQkoNCA8PCAxMCkKKyNkZWZpbmUg VkVDX0NPTkZJRzFfWV9DX0NWQlMJCSg1IDw8IDEwKQorI2RlZmluZSBWRUNfQ09ORklHMV9DX0NW QlNfWQkJKDYgPDwgMTApCisjZGVmaW5lIFZFQ19DT05GSUcxX0NfQ1ZCU19DVkJTCQkoNyA8PCAx MCkKKyNkZWZpbmUgVkVDX0NPTkZJRzFfRElTX0NIUgkJQklUKDkpCisjZGVmaW5lIFZFQ19DT05G SUcxX0RJU19MVU1BCQlCSVQoOCkKKyNkZWZpbmUgVkVDX0NPTkZJRzFfWUNCQ1JfSU4JCUJJVCg2 KQorI2RlZmluZSBWRUNfQ09ORklHMV9ESVRIRVJfVFlQRV9MRlNSCTAKKyNkZWZpbmUgVkVDX0NP TkZJRzFfRElUSEVSX1RZUEVfQ09VTlRFUglCSVQoNSkKKyNkZWZpbmUgVkVDX0NPTkZJRzFfRElU SEVSX0VOCQlCSVQoNCkKKyNkZWZpbmUgVkVDX0NPTkZJRzFfQ1lERUxBWQkJQklUKDMpCisjZGVm aW5lIFZFQ19DT05GSUcxX0xVTUFESVMJCUJJVCgyKQorI2RlZmluZSBWRUNfQ09ORklHMV9DT01Q RElTCQlCSVQoMSkKKyNkZWZpbmUgVkVDX0NPTkZJRzFfQ1VTVE9NX0ZSRVEJCUJJVCgwKQorCisj ZGVmaW5lIFZFQ19DT05GSUcyCQkJMHgxOGMKKyNkZWZpbmUgVkVDX0NPTkZJRzJfUFJPR19TQ0FO CQlCSVQoMTUpCisjZGVmaW5lIFZFQ19DT05GSUcyX1NZTkNfQURKX01BU0sJR0VOTUFTSygxNCwg MTIpCisjZGVmaW5lIFZFQ19DT05GSUcyX1NZTkNfQURKKHgpCQkoKCh4KSAvIDIpIDw8IDEyKQor I2RlZmluZSBWRUNfQ09ORklHMl9QQlBSX0VOCQlCSVQoMTApCisjZGVmaW5lIFZFQ19DT05GSUcy X1VWX0RJR19ESVMJCUJJVCg2KQorI2RlZmluZSBWRUNfQ09ORklHMl9SR0JfRElHX0RJUwkJQklU KDUpCisjZGVmaW5lIFZFQ19DT05GSUcyX1RNVVhfTUFTSwkJR0VOTUFTSygzLCAyKQorI2RlZmlu ZSBWRUNfQ09ORklHMl9UTVVYX0RSSVZFMAkJKDAgPDwgMikKKyNkZWZpbmUgVkVDX0NPTkZJRzJf VE1VWF9SR19DT01QCSgxIDw8IDIpCisjZGVmaW5lIFZFQ19DT05GSUcyX1RNVVhfVVZfWUMJCSgy IDw8IDIpCisjZGVmaW5lIFZFQ19DT05GSUcyX1RNVVhfU1lOQ19ZQwkoMyA8PCAyKQorCisjZGVm aW5lIFZFQ19JTlRFUlJVUFRfQ09OVFJPTAkJMHgxOTAKKyNkZWZpbmUgVkVDX0lOVEVSUlVQVF9T VEFUVVMJCTB4MTk0CisjZGVmaW5lIFZFQ19GQ1dfU0VDQU1fQgkJCTB4MTk4CisjZGVmaW5lIFZF Q19TRUNBTV9HQUlOX1ZBTAkJMHgxOWMKKworI2RlZmluZSBWRUNfQ09ORklHMwkJCTB4MWEwCisj ZGVmaW5lIFZFQ19DT05GSUczX0hPUklaX0xFTl9TVEQJKDAgPDwgMCkKKyNkZWZpbmUgVkVDX0NP TkZJRzNfSE9SSVpfTEVOX01QRUcxX1NJRgkoMSA8PCAwKQorI2RlZmluZSBWRUNfQ09ORklHM19T SEFQRV9OT05fTElORUFSCUJJVCgxKQorCisjZGVmaW5lIFZFQ19TVEFUVVMwCQkJMHgyMDAKKyNk ZWZpbmUgVkVDX01BU0swCQkJMHgyMDQKKworI2RlZmluZSBWRUNfQ0ZHCQkJCTB4MjA4CisjZGVm aW5lIFZFQ19DRkdfU0dfTU9ERV9NQVNLCQlHRU5NQVNLKDYsIDUpCisjZGVmaW5lIFZFQ19DRkdf U0dfTU9ERSh4KQkJKCh4KSA8PCA1KQorI2RlZmluZSBWRUNfQ0ZHX1NHX0VOCQkJQklUKDQpCisj ZGVmaW5lIFZFQ19DRkdfVkVDX0VOCQkJQklUKDMpCisjZGVmaW5lIFZFQ19DRkdfTUJfRU4JCQlC SVQoMikKKyNkZWZpbmUgVkVDX0NGR19FTkFCTEUJCQlCSVQoMSkKKyNkZWZpbmUgVkVDX0NGR19U Ql9FTgkJCUJJVCgwKQorCisjZGVmaW5lIFZFQ19EQUNfVEVTVAkJCTB4MjBjCisKKyNkZWZpbmUg VkVDX0RBQ19DT05GSUcJCQkweDIxMAorI2RlZmluZSBWRUNfREFDX0NPTkZJR19MRE9fQklBU19D VFJMKHgpCSgoeCkgPDwgMjQpCisjZGVmaW5lIFZFQ19EQUNfQ09ORklHX0RSSVZFUl9DVFJMKHgp CSgoeCkgPDwgMTYpCisjZGVmaW5lIFZFQ19EQUNfQ09ORklHX0RBQ19DVFJMKHgpCSh4KQorCisj ZGVmaW5lIFZFQ19EQUNfTUlTQwkJCTB4MjE0CisjZGVmaW5lIFZFQ19EQUNfTUlTQ19WQ0RfQ1RS TF9NQVNLCUdFTk1BU0soMzEsIDE2KQorI2RlZmluZSBWRUNfREFDX01JU0NfVkNEX0NUUkwoeCkJ KCh4KSA8PCAxNikKKyNkZWZpbmUgVkVDX0RBQ19NSVNDX1ZJRF9BQ1QJCUJJVCg4KQorI2RlZmlu ZSBWRUNfREFDX01JU0NfVkNEX1BXUkROCQlCSVQoNikKKyNkZWZpbmUgVkVDX0RBQ19NSVNDX0JJ QVNfUFdSRE4JCUJJVCg1KQorI2RlZmluZSBWRUNfREFDX01JU0NfREFDX1BXUkROCQlCSVQoMikK KyNkZWZpbmUgVkVDX0RBQ19NSVNDX0xET19QV1JETgkJQklUKDEpCisjZGVmaW5lIFZFQ19EQUNf TUlTQ19EQUNfUlNUX04JCUJJVCgwKQorCisKKy8qIEdlbmVyYWwgVkVDIGhhcmR3YXJlIHN0YXRl LiAqLworc3RydWN0IHZjNF92ZWMgeworCXN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXY7CisK KwlzdHJ1Y3QgZHJtX2VuY29kZXIgKmVuY29kZXI7CisJc3RydWN0IGRybV9jb25uZWN0b3IgKmNv bm5lY3RvcjsKKworCXZvaWQgX19pb21lbSAqcmVnczsKKworCXN0cnVjdCBjbGsgKmNsb2NrOwor CisJY29uc3Qgc3RydWN0IHZjNF92ZWNfdHZfbW9kZSAqdHZfbW9kZTsKK307CisKKyNkZWZpbmUg VkVDX1JFQUQob2Zmc2V0KSByZWFkbCh2ZWMtPnJlZ3MgKyAob2Zmc2V0KSkKKyNkZWZpbmUgVkVD X1dSSVRFKG9mZnNldCwgdmFsKSB3cml0ZWwodmFsLCB2ZWMtPnJlZ3MgKyAob2Zmc2V0KSkKKwor LyogVkM0IFZFQyBlbmNvZGVyIEtNUyBzdHJ1Y3QgKi8KK3N0cnVjdCB2YzRfdmVjX2VuY29kZXIg eworCXN0cnVjdCB2YzRfZW5jb2RlciBiYXNlOworCXN0cnVjdCB2YzRfdmVjICp2ZWM7Cit9Owor CitzdGF0aWMgaW5saW5lIHN0cnVjdCB2YzRfdmVjX2VuY29kZXIgKgordG9fdmM0X3ZlY19lbmNv ZGVyKHN0cnVjdCBkcm1fZW5jb2RlciAqZW5jb2RlcikKK3sKKwlyZXR1cm4gY29udGFpbmVyX29m KGVuY29kZXIsIHN0cnVjdCB2YzRfdmVjX2VuY29kZXIsIGJhc2UuYmFzZSk7Cit9CisKKy8qIFZD NCBWRUMgY29ubmVjdG9yIEtNUyBzdHJ1Y3QgKi8KK3N0cnVjdCB2YzRfdmVjX2Nvbm5lY3RvciB7 CisJc3RydWN0IGRybV9jb25uZWN0b3IgYmFzZTsKKwlzdHJ1Y3QgdmM0X3ZlYyAqdmVjOworCisJ LyogU2luY2UgdGhlIGNvbm5lY3RvciBpcyBhdHRhY2hlZCB0byBqdXN0IHRoZSBvbmUgZW5jb2Rl ciwKKwkgKiB0aGlzIGlzIHRoZSByZWZlcmVuY2UgdG8gaXQgc28gd2UgY2FuIGRvIHRoZSBiZXN0 X2VuY29kZXIoKQorCSAqIGhvb2suCisJICovCisJc3RydWN0IGRybV9lbmNvZGVyICplbmNvZGVy OworfTsKKworc3RhdGljIGlubGluZSBzdHJ1Y3QgdmM0X3ZlY19jb25uZWN0b3IgKgordG9fdmM0 X3ZlY19jb25uZWN0b3Ioc3RydWN0IGRybV9jb25uZWN0b3IgKmNvbm5lY3RvcikKK3sKKwlyZXR1 cm4gY29udGFpbmVyX29mKGNvbm5lY3Rvciwgc3RydWN0IHZjNF92ZWNfY29ubmVjdG9yLCBiYXNl KTsKK30KKworZW51bSB2YzRfdmVjX3R2X21vZGVfaWQgeworCVZDNF9WRUNfVFZfTU9ERV9OVFND LAorCVZDNF9WRUNfVFZfTU9ERV9OVFNDX0osCisJVkM0X1ZFQ19UVl9NT0RFX1BBTCwKKwlWQzRf VkVDX1RWX01PREVfUEFMX00sCit9OworCitzdHJ1Y3QgdmM0X3ZlY190dl9tb2RlIHsKKwljb25z dCBzdHJ1Y3QgZHJtX2Rpc3BsYXlfbW9kZSAqbW9kZTsKKwl2b2lkICgqbW9kZV9zZXQpKHN0cnVj dCB2YzRfdmVjICp2ZWMpOworfTsKKworI2RlZmluZSBWRUNfUkVHKHJlZykgeyByZWcsICNyZWcg fQorc3RhdGljIGNvbnN0IHN0cnVjdCB7CisJdTMyIHJlZzsKKwljb25zdCBjaGFyICpuYW1lOwor fSB2ZWNfcmVnc1tdID0geworCVZFQ19SRUcoVkVDX1dTRV9DT05UUk9MKSwKKwlWRUNfUkVHKFZF Q19XU0VfV1NTX0RBVEEpLAorCVZFQ19SRUcoVkVDX1dTRV9WUFNfREFUQTEpLAorCVZFQ19SRUco VkVDX1dTRV9WUFNfQ09OVFJPTCksCisJVkVDX1JFRyhWRUNfUkVWSUQpLAorCVZFQ19SRUcoVkVD X0NPTkZJRzApLAorCVZFQ19SRUcoVkVDX1NDSFBIKSwKKwlWRUNfUkVHKFZFQ19DTE1QMF9TVEFS VCksCisJVkVDX1JFRyhWRUNfQ0xNUDBfRU5EKSwKKwlWRUNfUkVHKFZFQ19GUkVRM18yKSwKKwlW RUNfUkVHKFZFQ19GUkVRMV8wKSwKKwlWRUNfUkVHKFZFQ19DT05GSUcxKSwKKwlWRUNfUkVHKFZF Q19DT05GSUcyKSwKKwlWRUNfUkVHKFZFQ19JTlRFUlJVUFRfQ09OVFJPTCksCisJVkVDX1JFRyhW RUNfSU5URVJSVVBUX1NUQVRVUyksCisJVkVDX1JFRyhWRUNfRkNXX1NFQ0FNX0IpLAorCVZFQ19S RUcoVkVDX1NFQ0FNX0dBSU5fVkFMKSwKKwlWRUNfUkVHKFZFQ19DT05GSUczKSwKKwlWRUNfUkVH KFZFQ19TVEFUVVMwKSwKKwlWRUNfUkVHKFZFQ19NQVNLMCksCisJVkVDX1JFRyhWRUNfQ0ZHKSwK KwlWRUNfUkVHKFZFQ19EQUNfVEVTVCksCisJVkVDX1JFRyhWRUNfREFDX0NPTkZJRyksCisJVkVD X1JFRyhWRUNfREFDX01JU0MpLAorfTsKKworI2lmZGVmIENPTkZJR19ERUJVR19GUworaW50IHZj NF92ZWNfZGVidWdmc19yZWdzKHN0cnVjdCBzZXFfZmlsZSAqbSwgdm9pZCAqdW51c2VkKQorewor CXN0cnVjdCBkcm1faW5mb19ub2RlICpub2RlID0gKHN0cnVjdCBkcm1faW5mb19ub2RlICopbS0+ cHJpdmF0ZTsKKwlzdHJ1Y3QgZHJtX2RldmljZSAqZGV2ID0gbm9kZS0+bWlub3ItPmRldjsKKwlz dHJ1Y3QgdmM0X2RldiAqdmM0ID0gdG9fdmM0X2RldihkZXYpOworCXN0cnVjdCB2YzRfdmVjICp2 ZWMgPSB2YzQtPnZlYzsKKwlpbnQgaTsKKworCWlmICghdmVjKQorCQlyZXR1cm4gMDsKKworCWZv ciAoaSA9IDA7IGkgPCBBUlJBWV9TSVpFKHZlY19yZWdzKTsgaSsrKSB7CisJCXNlcV9wcmludGYo bSwgIiVzICgweCUwNHgpOiAweCUwOHhcbiIsCisJCQkgICB2ZWNfcmVnc1tpXS5uYW1lLCB2ZWNf cmVnc1tpXS5yZWcsCisJCQkgICBWRUNfUkVBRCh2ZWNfcmVnc1tpXS5yZWcpKTsKKwl9CisKKwly ZXR1cm4gMDsKK30KKyNlbmRpZgorCitzdGF0aWMgdm9pZCB2YzRfdmVjX250c2NfbW9kZV9zZXQo c3RydWN0IHZjNF92ZWMgKnZlYykKK3sKKwlWRUNfV1JJVEUoVkVDX0NPTkZJRzAsIFZFQ19DT05G SUcwX05UU0NfU1REIHwgVkVDX0NPTkZJRzBfUERFTik7CisJVkVDX1dSSVRFKFZFQ19DT05GSUcx LCBWRUNfQ09ORklHMV9DX0NWQlNfQ1ZCUyk7Cit9CisKK3N0YXRpYyB2b2lkIHZjNF92ZWNfbnRz Y19qX21vZGVfc2V0KHN0cnVjdCB2YzRfdmVjICp2ZWMpCit7CisJVkVDX1dSSVRFKFZFQ19DT05G SUcwLCBWRUNfQ09ORklHMF9OVFNDX1NURCk7CisJVkVDX1dSSVRFKFZFQ19DT05GSUcxLCBWRUNf Q09ORklHMV9DX0NWQlNfQ1ZCUyk7Cit9CisKK3N0YXRpYyBjb25zdCBzdHJ1Y3QgZHJtX2Rpc3Bs YXlfbW9kZSBudHNjX21vZGUgPSB7CisJRFJNX01PREUoIjcyMHg0ODAiLCBEUk1fTU9ERV9UWVBF X0RSSVZFUiwgMTM1MDAsCisJCSA3MjAsIDcyMCArIDE0LCA3MjAgKyAxNCArIDY0LCA3MjAgKyAx NCArIDY0ICsgNjAsIDAsCisJCSA0ODAsIDQ4MCArIDMsIDQ4MCArIDMgKyAzLCA0ODAgKyAzICsg MyArIDE2LCAwLAorCQkgRFJNX01PREVfRkxBR19JTlRFUkxBQ0UpCit9OworCitzdGF0aWMgdm9p ZCB2YzRfdmVjX3BhbF9tb2RlX3NldChzdHJ1Y3QgdmM0X3ZlYyAqdmVjKQoreworCVZFQ19XUklU RShWRUNfQ09ORklHMCwgVkVDX0NPTkZJRzBfUEFMX0JER0hJX1NURCk7CisJVkVDX1dSSVRFKFZF Q19DT05GSUcxLCBWRUNfQ09ORklHMV9DX0NWQlNfQ1ZCUyk7Cit9CisKK3N0YXRpYyB2b2lkIHZj NF92ZWNfcGFsX21fbW9kZV9zZXQoc3RydWN0IHZjNF92ZWMgKnZlYykKK3sKKwlWRUNfV1JJVEUo VkVDX0NPTkZJRzAsIFZFQ19DT05GSUcwX1BBTF9CREdISV9TVEQpOworCVZFQ19XUklURShWRUNf Q09ORklHMSwKKwkJICBWRUNfQ09ORklHMV9DX0NWQlNfQ1ZCUyB8IFZFQ19DT05GSUcxX0NVU1RP TV9GUkVRKTsKKwlWRUNfV1JJVEUoVkVDX0ZSRVEzXzIsIDB4MjIzYik7CisJVkVDX1dSSVRFKFZF Q19GUkVRMV8wLCAweDYxZDEpOworfQorCitzdGF0aWMgY29uc3Qgc3RydWN0IGRybV9kaXNwbGF5 X21vZGUgcGFsX21vZGUgPSB7CisJRFJNX01PREUoIjcyMHg1NzYiLCBEUk1fTU9ERV9UWVBFX0RS SVZFUiwgMTM1MDAsCisJCSA3MjAsIDcyMCArIDIwLCA3MjAgKyAyMCArIDY0LCA3MjAgKyAyMCAr IDY0ICsgNjAsIDAsCisJCSA1NzYsIDU3NiArIDIsIDU3NiArIDIgKyAzLCA1NzYgKyAyICsgMyAr IDIwLCAwLAorCQkgRFJNX01PREVfRkxBR19JTlRFUkxBQ0UpCit9OworCitzdGF0aWMgY29uc3Qg c3RydWN0IHZjNF92ZWNfdHZfbW9kZSB2YzRfdmVjX3R2X21vZGVzW10gPSB7CisJW1ZDNF9WRUNf VFZfTU9ERV9OVFNDXSA9IHsKKwkJLm1vZGUgPSAmbnRzY19tb2RlLAorCQkubW9kZV9zZXQgPSB2 YzRfdmVjX250c2NfbW9kZV9zZXQsCisJfSwKKwlbVkM0X1ZFQ19UVl9NT0RFX05UU0NfSl0gPSB7 CisJCS5tb2RlID0gJm50c2NfbW9kZSwKKwkJLm1vZGVfc2V0ID0gdmM0X3ZlY19udHNjX2pfbW9k ZV9zZXQsCisJfSwKKwlbVkM0X1ZFQ19UVl9NT0RFX1BBTF0gPSB7CisJCS5tb2RlID0gJnBhbF9t b2RlLAorCQkubW9kZV9zZXQgPSB2YzRfdmVjX3BhbF9tb2RlX3NldCwKKwl9LAorCVtWQzRfVkVD X1RWX01PREVfUEFMX01dID0geworCQkubW9kZSA9ICZwYWxfbW9kZSwKKwkJLm1vZGVfc2V0ID0g dmM0X3ZlY19wYWxfbV9tb2RlX3NldCwKKwl9LAorfTsKKworc3RhdGljIGVudW0gZHJtX2Nvbm5l Y3Rvcl9zdGF0dXMKK3ZjNF92ZWNfY29ubmVjdG9yX2RldGVjdChzdHJ1Y3QgZHJtX2Nvbm5lY3Rv ciAqY29ubmVjdG9yLCBib29sIGZvcmNlKQoreworCXJldHVybiBjb25uZWN0b3Jfc3RhdHVzX3Vu a25vd247Cit9CisKK3N0YXRpYyB2b2lkIHZjNF92ZWNfY29ubmVjdG9yX2Rlc3Ryb3koc3RydWN0 IGRybV9jb25uZWN0b3IgKmNvbm5lY3RvcikKK3sKKwlkcm1fY29ubmVjdG9yX3VucmVnaXN0ZXIo Y29ubmVjdG9yKTsKKwlkcm1fY29ubmVjdG9yX2NsZWFudXAoY29ubmVjdG9yKTsKK30KKworc3Rh dGljIGludCB2YzRfdmVjX2Nvbm5lY3Rvcl9nZXRfbW9kZXMoc3RydWN0IGRybV9jb25uZWN0b3Ig KmNvbm5lY3RvcikKK3sKKwlzdHJ1Y3QgZHJtX2Nvbm5lY3Rvcl9zdGF0ZSAqc3RhdGUgPSBjb25u ZWN0b3ItPnN0YXRlOworCXN0cnVjdCBkcm1fZGlzcGxheV9tb2RlICptb2RlOworCisJbW9kZSA9 IGRybV9tb2RlX2R1cGxpY2F0ZShjb25uZWN0b3ItPmRldiwKKwkJCQkgIHZjNF92ZWNfdHZfbW9k ZXNbc3RhdGUtPnR2Lm1vZGVdLm1vZGUpOworCWlmICghbW9kZSkgeworCQlEUk1fRVJST1IoIkZh aWxlZCB0byBjcmVhdGUgYSBuZXcgZGlzcGxheSBtb2RlXG4iKTsKKwkJcmV0dXJuIC1FTk9NRU07 CisJfQorCisJZHJtX21vZGVfcHJvYmVkX2FkZChjb25uZWN0b3IsIG1vZGUpOworCisJcmV0dXJu IDE7Cit9CisKK3N0YXRpYyBjb25zdCBzdHJ1Y3QgZHJtX2Nvbm5lY3Rvcl9mdW5jcyB2YzRfdmVj X2Nvbm5lY3Rvcl9mdW5jcyA9IHsKKwkuZHBtcyA9IGRybV9hdG9taWNfaGVscGVyX2Nvbm5lY3Rv cl9kcG1zLAorCS5kZXRlY3QgPSB2YzRfdmVjX2Nvbm5lY3Rvcl9kZXRlY3QsCisJLmZpbGxfbW9k ZXMgPSBkcm1faGVscGVyX3Byb2JlX3NpbmdsZV9jb25uZWN0b3JfbW9kZXMsCisJLnNldF9wcm9w ZXJ0eSA9IGRybV9hdG9taWNfaGVscGVyX2Nvbm5lY3Rvcl9zZXRfcHJvcGVydHksCisJLmRlc3Ry b3kgPSB2YzRfdmVjX2Nvbm5lY3Rvcl9kZXN0cm95LAorCS5yZXNldCA9IGRybV9hdG9taWNfaGVs cGVyX2Nvbm5lY3Rvcl9yZXNldCwKKwkuYXRvbWljX2R1cGxpY2F0ZV9zdGF0ZSA9IGRybV9hdG9t aWNfaGVscGVyX2Nvbm5lY3Rvcl9kdXBsaWNhdGVfc3RhdGUsCisJLmF0b21pY19kZXN0cm95X3N0 YXRlID0gZHJtX2F0b21pY19oZWxwZXJfY29ubmVjdG9yX2Rlc3Ryb3lfc3RhdGUsCit9OworCitz dGF0aWMgY29uc3Qgc3RydWN0IGRybV9jb25uZWN0b3JfaGVscGVyX2Z1bmNzIHZjNF92ZWNfY29u bmVjdG9yX2hlbHBlcl9mdW5jcyA9IHsKKwkuZ2V0X21vZGVzID0gdmM0X3ZlY19jb25uZWN0b3Jf Z2V0X21vZGVzLAorfTsKKworc3RhdGljIHN0cnVjdCBkcm1fY29ubmVjdG9yICp2YzRfdmVjX2Nv bm5lY3Rvcl9pbml0KHN0cnVjdCBkcm1fZGV2aWNlICpkZXYsCisJCQkJCQkgICAgc3RydWN0IHZj NF92ZWMgKnZlYykKK3sKKwlzdHJ1Y3QgZHJtX2Nvbm5lY3RvciAqY29ubmVjdG9yID0gTlVMTDsK KwlzdHJ1Y3QgdmM0X3ZlY19jb25uZWN0b3IgKnZlY19jb25uZWN0b3I7CisKKwl2ZWNfY29ubmVj dG9yID0gZGV2bV9remFsbG9jKGRldi0+ZGV2LCBzaXplb2YoKnZlY19jb25uZWN0b3IpLAorCQkJ CSAgICAgR0ZQX0tFUk5FTCk7CisJaWYgKCF2ZWNfY29ubmVjdG9yKQorCQlyZXR1cm4gRVJSX1BU UigtRU5PTUVNKTsKKworCWNvbm5lY3RvciA9ICZ2ZWNfY29ubmVjdG9yLT5iYXNlOworCWNvbm5l Y3Rvci0+aW50ZXJsYWNlX2FsbG93ZWQgPSB0cnVlOworCisJdmVjX2Nvbm5lY3Rvci0+ZW5jb2Rl ciA9IHZlYy0+ZW5jb2RlcjsKKwl2ZWNfY29ubmVjdG9yLT52ZWMgPSB2ZWM7CisKKwlkcm1fY29u bmVjdG9yX2luaXQoZGV2LCBjb25uZWN0b3IsICZ2YzRfdmVjX2Nvbm5lY3Rvcl9mdW5jcywKKwkJ CSAgIERSTV9NT0RFX0NPTk5FQ1RPUl9Db21wb3NpdGUpOworCWRybV9jb25uZWN0b3JfaGVscGVy X2FkZChjb25uZWN0b3IsICZ2YzRfdmVjX2Nvbm5lY3Rvcl9oZWxwZXJfZnVuY3MpOworCisJZHJt X29iamVjdF9hdHRhY2hfcHJvcGVydHkoJmNvbm5lY3Rvci0+YmFzZSwKKwkJCQkgICBkZXYtPm1v ZGVfY29uZmlnLnR2X21vZGVfcHJvcGVydHksCisJCQkJICAgVkM0X1ZFQ19UVl9NT0RFX05UU0Mp OworCXZlYy0+dHZfbW9kZSA9ICZ2YzRfdmVjX3R2X21vZGVzW1ZDNF9WRUNfVFZfTU9ERV9OVFND XTsKKworCWRybV9tb2RlX2Nvbm5lY3Rvcl9hdHRhY2hfZW5jb2Rlcihjb25uZWN0b3IsIHZlYy0+ ZW5jb2Rlcik7CisKKwlyZXR1cm4gY29ubmVjdG9yOworfQorCitzdGF0aWMgY29uc3Qgc3RydWN0 IGRybV9lbmNvZGVyX2Z1bmNzIHZjNF92ZWNfZW5jb2Rlcl9mdW5jcyA9IHsKKwkuZGVzdHJveSA9 IGRybV9lbmNvZGVyX2NsZWFudXAsCit9OworCitzdGF0aWMgdm9pZCB2YzRfdmVjX2VuY29kZXJf ZGlzYWJsZShzdHJ1Y3QgZHJtX2VuY29kZXIgKmVuY29kZXIpCit7CisJc3RydWN0IHZjNF92ZWNf ZW5jb2RlciAqdmM0X3ZlY19lbmNvZGVyID0gdG9fdmM0X3ZlY19lbmNvZGVyKGVuY29kZXIpOwor CXN0cnVjdCB2YzRfdmVjICp2ZWMgPSB2YzRfdmVjX2VuY29kZXItPnZlYzsKKwlpbnQgcmV0Owor CisJVkVDX1dSSVRFKFZFQ19DRkcsIDApOworCVZFQ19XUklURShWRUNfREFDX01JU0MsCisJCSAg VkVDX0RBQ19NSVNDX1ZDRF9QV1JETiB8CisJCSAgVkVDX0RBQ19NSVNDX0JJQVNfUFdSRE4gfAor CQkgIFZFQ19EQUNfTUlTQ19EQUNfUFdSRE4gfAorCQkgIFZFQ19EQUNfTUlTQ19MRE9fUFdSRE4p OworCisJY2xrX2Rpc2FibGVfdW5wcmVwYXJlKHZlYy0+Y2xvY2spOworCisJcmV0ID0gcG1fcnVu dGltZV9wdXQoJnZlYy0+cGRldi0+ZGV2KTsKKwlpZiAocmV0IDwgMCkgeworCQlEUk1fRVJST1Io IkZhaWxlZCB0byByZWxlYXNlIHBvd2VyIGRvbWFpbjogJWRcbiIsIHJldCk7CisJCXJldHVybjsK Kwl9Cit9CisKK3N0YXRpYyB2b2lkIHZjNF92ZWNfZW5jb2Rlcl9lbmFibGUoc3RydWN0IGRybV9l bmNvZGVyICplbmNvZGVyKQoreworCXN0cnVjdCB2YzRfdmVjX2VuY29kZXIgKnZjNF92ZWNfZW5j b2RlciA9IHRvX3ZjNF92ZWNfZW5jb2RlcihlbmNvZGVyKTsKKwlzdHJ1Y3QgdmM0X3ZlYyAqdmVj ID0gdmM0X3ZlY19lbmNvZGVyLT52ZWM7CisJaW50IHJldDsKKworCXJldCA9IHBtX3J1bnRpbWVf Z2V0X3N5bmMoJnZlYy0+cGRldi0+ZGV2KTsKKwlpZiAocmV0IDwgMCkgeworCQlEUk1fRVJST1Io IkZhaWxlZCB0byByZXRhaW4gcG93ZXIgZG9tYWluOiAlZFxuIiwgcmV0KTsKKwkJcmV0dXJuOwor CX0KKworCS8qCisJICogV2UgbmVlZCB0byBzZXQgdGhlIGNsb2NrIHJhdGUgZWFjaCB0aW1lIHdl IGVuYWJsZSB0aGUgZW5jb2RlcgorCSAqIGJlY2F1c2UgdGhlcmUncyBhIGNoYW5jZSB3ZSBzaGFy ZSB0aGUgc2FtZSBwYXJlbnQgd2l0aCB0aGUgSERNSQorCSAqIGNsb2NrLCBhbmQgYm90aCBkcml2 ZXJzIGFyZSByZXF1ZXN0aW5nIGRpZmZlcmVudCByYXRlcy4KKwkgKiBUaGUgZ29vZCBuZXdzIGlz LCB0aGVzZSAyIGVuY29kZXJzIGNhbm5vdCBiZSBlbmFibGVkIGF0IHRoZSBzYW1lCisJICogdGlt ZSwgdGh1cyBwcmV2ZW50aW5nIGluY29tcGF0aWJsZSByYXRlIHJlcXVlc3RzLgorCSAqLworCXJl dCA9IGNsa19zZXRfcmF0ZSh2ZWMtPmNsb2NrLCAxMDgwMDAwMDApOworCWlmIChyZXQpIHsKKwkJ RFJNX0VSUk9SKCJGYWlsZWQgdG8gc2V0IGNsb2NrIHJhdGU6ICVkXG4iLCByZXQpOworCQlyZXR1 cm47CisJfQorCisJcmV0ID0gY2xrX3ByZXBhcmVfZW5hYmxlKHZlYy0+Y2xvY2spOworCWlmIChy ZXQpIHsKKwkJRFJNX0VSUk9SKCJGYWlsZWQgdG8gdHVybiBvbiBjb3JlIGNsb2NrOiAlZFxuIiwg cmV0KTsKKwkJcmV0dXJuOworCX0KKworCS8qIFJlc2V0IHRoZSBkaWZmZXJlbnQgYmxvY2tzICov CisJVkVDX1dSSVRFKFZFQ19XU0VfUkVTRVQsIDEpOworCVZFQ19XUklURShWRUNfU09GVF9SRVNF VCwgMSk7CisKKwkvKiBEaXNhYmxlIHRoZSBDR1NNLUEgYW5kIFdTRSBibG9ja3MgKi8KKwlWRUNf V1JJVEUoVkVDX1dTRV9DT05UUk9MLCAwKTsKKworCS8qIFdyaXRlIGNvbmZpZyBjb21tb24gdG8g YWxsIG1vZGVzLiAqLworCisJLyoKKwkgKiBDb2xvciBzdWJjYXJyaWVyIHBoYXNlOiBwaGFzZSA9 IDM2MCAqIFNDSFBIIC8gMjU2LgorCSAqIDB4MjggPD0+IDM5LjM3NSBkZWcuCisJICovCisJVkVD X1dSSVRFKFZFQ19TQ0hQSCwgMHgyOCk7CisKKwkvKgorCSAqIFJlc2V0IHRvIGRlZmF1bHQgdmFs dWVzLgorCSAqLworCVZFQ19XUklURShWRUNfQ0xNUDBfU1RBUlQsIDB4YWMpOworCVZFQ19XUklU RShWRUNfQ0xNUDBfRU5ELCAweGVjKTsKKwlWRUNfV1JJVEUoVkVDX0NPTkZJRzIsCisJCSAgVkVD X0NPTkZJRzJfVVZfRElHX0RJUyB8IFZFQ19DT05GSUcyX1JHQl9ESUdfRElTKTsKKwlWRUNfV1JJ VEUoVkVDX0NPTkZJRzMsIFZFQ19DT05GSUczX0hPUklaX0xFTl9TVEQpOworCVZFQ19XUklURShW RUNfREFDX0NPTkZJRywKKwkJICBWRUNfREFDX0NPTkZJR19EQUNfQ1RSTCgweGMpIHwKKwkJICBW RUNfREFDX0NPTkZJR19EUklWRVJfQ1RSTCgweGMpIHwKKwkJICBWRUNfREFDX0NPTkZJR19MRE9f QklBU19DVFJMKDB4NDYpKTsKKworCS8qIE1hc2sgYWxsIGludGVycnVwdHMuICovCisJVkVDX1dS SVRFKFZFQ19NQVNLMCwgMCk7CisKKwl2ZWMtPnR2X21vZGUtPm1vZGVfc2V0KHZlYyk7CisKKwlW RUNfV1JJVEUoVkVDX0RBQ19NSVNDLAorCQkgIFZFQ19EQUNfTUlTQ19WSURfQUNUIHwgVkVDX0RB Q19NSVNDX0RBQ19SU1RfTik7CisJVkVDX1dSSVRFKFZFQ19DRkcsIFZFQ19DRkdfVkVDX0VOKTsK K30KKworCitzdGF0aWMgYm9vbCB2YzRfdmVjX2VuY29kZXJfbW9kZV9maXh1cChzdHJ1Y3QgZHJt X2VuY29kZXIgKmVuY29kZXIsCisJCQkJICAgICAgIGNvbnN0IHN0cnVjdCBkcm1fZGlzcGxheV9t b2RlICptb2RlLAorCQkJCSAgICAgICBzdHJ1Y3QgZHJtX2Rpc3BsYXlfbW9kZSAqYWRqdXN0ZWRf bW9kZSkKK3sKKwlyZXR1cm4gdHJ1ZTsKK30KKworc3RhdGljIHZvaWQgdmM0X3ZlY19lbmNvZGVy X2F0b21pY19tb2RlX3NldChzdHJ1Y3QgZHJtX2VuY29kZXIgKmVuY29kZXIsCisJCQkJCXN0cnVj dCBkcm1fY3J0Y19zdGF0ZSAqY3J0Y19zdGF0ZSwKKwkJCQkJc3RydWN0IGRybV9jb25uZWN0b3Jf c3RhdGUgKmNvbm5fc3RhdGUpCit7CisJc3RydWN0IHZjNF92ZWNfZW5jb2RlciAqdmM0X3ZlY19l bmNvZGVyID0gdG9fdmM0X3ZlY19lbmNvZGVyKGVuY29kZXIpOworCXN0cnVjdCB2YzRfdmVjICp2 ZWMgPSB2YzRfdmVjX2VuY29kZXItPnZlYzsKKworCXZlYy0+dHZfbW9kZSA9ICZ2YzRfdmVjX3R2 X21vZGVzW2Nvbm5fc3RhdGUtPnR2Lm1vZGVdOworfQorCitzdGF0aWMgaW50IHZjNF92ZWNfZW5j b2Rlcl9hdG9taWNfY2hlY2soc3RydWN0IGRybV9lbmNvZGVyICplbmNvZGVyLAorCQkJCQlzdHJ1 Y3QgZHJtX2NydGNfc3RhdGUgKmNydGNfc3RhdGUsCisJCQkJCXN0cnVjdCBkcm1fY29ubmVjdG9y X3N0YXRlICpjb25uX3N0YXRlKQoreworCWNvbnN0IHN0cnVjdCB2YzRfdmVjX3R2X21vZGUgKnZl Y19tb2RlOworCisJdmVjX21vZGUgPSAmdmM0X3ZlY190dl9tb2Rlc1tjb25uX3N0YXRlLT50di5t b2RlXTsKKworCWlmIChjb25uX3N0YXRlLT5jcnRjICYmCisJICAgICFkcm1fbW9kZV9lcXVhbCh2 ZWNfbW9kZS0+bW9kZSwgJmNydGNfc3RhdGUtPmFkanVzdGVkX21vZGUpKQorCQlyZXR1cm4gLUVJ TlZBTDsKKworCXJldHVybiAwOworfQorCitzdGF0aWMgY29uc3Qgc3RydWN0IGRybV9lbmNvZGVy X2hlbHBlcl9mdW5jcyB2YzRfdmVjX2VuY29kZXJfaGVscGVyX2Z1bmNzID0geworCS5kaXNhYmxl ID0gdmM0X3ZlY19lbmNvZGVyX2Rpc2FibGUsCisJLmVuYWJsZSA9IHZjNF92ZWNfZW5jb2Rlcl9l bmFibGUsCisJLm1vZGVfZml4dXAgPSB2YzRfdmVjX2VuY29kZXJfbW9kZV9maXh1cCwKKwkuYXRv bWljX2NoZWNrID0gdmM0X3ZlY19lbmNvZGVyX2F0b21pY19jaGVjaywKKwkuYXRvbWljX21vZGVf c2V0ID0gdmM0X3ZlY19lbmNvZGVyX2F0b21pY19tb2RlX3NldCwKK307CisKK3N0YXRpYyBjb25z dCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkIHZjNF92ZWNfZHRfbWF0Y2hbXSA9IHsKKwl7IC5jb21wYXRp YmxlID0gImJyY20sYmNtMjgzNS12ZWMiLCAuZGF0YSA9IE5VTEwgfSwKKwl7IC8qIHNlbnRpbmVs ICovIH0sCit9OworCitzdGF0aWMgY29uc3QgY2hhciAqIGNvbnN0IHR2X21vZGVfbmFtZXNbXSA9 IHsKKwlbVkM0X1ZFQ19UVl9NT0RFX05UU0NdID0gIk5UU0MiLAorCVtWQzRfVkVDX1RWX01PREVf TlRTQ19KXSA9ICJOVFNDLUoiLAorCVtWQzRfVkVDX1RWX01PREVfUEFMXSA9ICJQQUwiLAorCVtW QzRfVkVDX1RWX01PREVfUEFMX01dID0gIlBBTC1NIiwKK307CisKK3N0YXRpYyBpbnQgdmM0X3Zl Y19iaW5kKHN0cnVjdCBkZXZpY2UgKmRldiwgc3RydWN0IGRldmljZSAqbWFzdGVyLCB2b2lkICpk YXRhKQoreworCXN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYgPSB0b19wbGF0Zm9ybV9kZXZp Y2UoZGV2KTsKKwlzdHJ1Y3QgZHJtX2RldmljZSAqZHJtID0gZGV2X2dldF9kcnZkYXRhKG1hc3Rl cik7CisJc3RydWN0IHZjNF9kZXYgKnZjNCA9IHRvX3ZjNF9kZXYoZHJtKTsKKwlzdHJ1Y3QgdmM0 X3ZlYyAqdmVjOworCXN0cnVjdCB2YzRfdmVjX2VuY29kZXIgKnZjNF92ZWNfZW5jb2RlcjsKKwlp bnQgcmV0OworCisJcmV0ID0gZHJtX21vZGVfY3JlYXRlX3R2X3Byb3BlcnRpZXMoZHJtLCBBUlJB WV9TSVpFKHR2X21vZGVfbmFtZXMpLAorCQkJCQkgICAgdHZfbW9kZV9uYW1lcyk7CisJaWYgKHJl dCkKKwkJcmV0dXJuIHJldDsKKworCXZlYyA9IGRldm1fa3phbGxvYyhkZXYsIHNpemVvZigqdmVj KSwgR0ZQX0tFUk5FTCk7CisJaWYgKCF2ZWMpCisJCXJldHVybiAtRU5PTUVNOworCisJdmM0X3Zl Y19lbmNvZGVyID0gZGV2bV9remFsbG9jKGRldiwgc2l6ZW9mKCp2YzRfdmVjX2VuY29kZXIpLAor CQkJCSAgICAgICBHRlBfS0VSTkVMKTsKKwlpZiAoIXZjNF92ZWNfZW5jb2RlcikKKwkJcmV0dXJu IC1FTk9NRU07CisJdmM0X3ZlY19lbmNvZGVyLT5iYXNlLnR5cGUgPSBWQzRfRU5DT0RFUl9UWVBF X1ZFQzsKKwl2YzRfdmVjX2VuY29kZXItPnZlYyA9IHZlYzsKKwl2ZWMtPmVuY29kZXIgPSAmdmM0 X3ZlY19lbmNvZGVyLT5iYXNlLmJhc2U7CisKKwl2ZWMtPnBkZXYgPSBwZGV2OworCXZlYy0+cmVn cyA9IHZjNF9pb3JlbWFwX3JlZ3MocGRldiwgMCk7CisJaWYgKElTX0VSUih2ZWMtPnJlZ3MpKQor CQlyZXR1cm4gUFRSX0VSUih2ZWMtPnJlZ3MpOworCisJdmVjLT5jbG9jayA9IGRldm1fY2xrX2dl dChkZXYsIE5VTEwpOworCWlmIChJU19FUlIodmVjLT5jbG9jaykpIHsKKwkJcmV0ID0gUFRSX0VS Uih2ZWMtPmNsb2NrKTsKKwkJaWYgKHJldCAhPSAtRVBST0JFX0RFRkVSKQorCQkJRFJNX0VSUk9S KCJGYWlsZWQgdG8gZ2V0IGNsb2NrOiAlZFxuIiwgcmV0KTsKKwkJcmV0dXJuIHJldDsKKwl9CisK KwlwbV9ydW50aW1lX2VuYWJsZShkZXYpOworCisJZHJtX2VuY29kZXJfaW5pdChkcm0sIHZlYy0+ ZW5jb2RlciwgJnZjNF92ZWNfZW5jb2Rlcl9mdW5jcywKKwkJCSBEUk1fTU9ERV9FTkNPREVSX1RW REFDLCBOVUxMKTsKKwlkcm1fZW5jb2Rlcl9oZWxwZXJfYWRkKHZlYy0+ZW5jb2RlciwgJnZjNF92 ZWNfZW5jb2Rlcl9oZWxwZXJfZnVuY3MpOworCisJdmVjLT5jb25uZWN0b3IgPSB2YzRfdmVjX2Nv bm5lY3Rvcl9pbml0KGRybSwgdmVjKTsKKwlpZiAoSVNfRVJSKHZlYy0+Y29ubmVjdG9yKSkgewor CQlyZXQgPSBQVFJfRVJSKHZlYy0+Y29ubmVjdG9yKTsKKwkJZ290byBlcnJfZGVzdHJveV9lbmNv ZGVyOworCX0KKworCWRldl9zZXRfZHJ2ZGF0YShkZXYsIHZlYyk7CisKKwl2YzQtPnZlYyA9IHZl YzsKKworCXJldHVybiAwOworCitlcnJfZGVzdHJveV9lbmNvZGVyOgorCWRybV9lbmNvZGVyX2Ns ZWFudXAodmVjLT5lbmNvZGVyKTsKKwlwbV9ydW50aW1lX2Rpc2FibGUoZGV2KTsKKworCXJldHVy biByZXQ7Cit9CisKK3N0YXRpYyB2b2lkIHZjNF92ZWNfdW5iaW5kKHN0cnVjdCBkZXZpY2UgKmRl diwgc3RydWN0IGRldmljZSAqbWFzdGVyLAorCQkJICAgdm9pZCAqZGF0YSkKK3sKKwlzdHJ1Y3Qg ZHJtX2RldmljZSAqZHJtID0gZGV2X2dldF9kcnZkYXRhKG1hc3Rlcik7CisJc3RydWN0IHZjNF9k ZXYgKnZjNCA9IHRvX3ZjNF9kZXYoZHJtKTsKKwlzdHJ1Y3QgdmM0X3ZlYyAqdmVjID0gZGV2X2dl dF9kcnZkYXRhKGRldik7CisKKwl2YzRfdmVjX2Nvbm5lY3Rvcl9kZXN0cm95KHZlYy0+Y29ubmVj dG9yKTsKKwlkcm1fZW5jb2Rlcl9jbGVhbnVwKHZlYy0+ZW5jb2Rlcik7CisJcG1fcnVudGltZV9k aXNhYmxlKGRldik7CisKKwl2YzQtPnZlYyA9IE5VTEw7Cit9CisKK3N0YXRpYyBjb25zdCBzdHJ1 Y3QgY29tcG9uZW50X29wcyB2YzRfdmVjX29wcyA9IHsKKwkuYmluZCAgID0gdmM0X3ZlY19iaW5k LAorCS51bmJpbmQgPSB2YzRfdmVjX3VuYmluZCwKK307CisKK3N0YXRpYyBpbnQgdmM0X3ZlY19k ZXZfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikKK3sKKwlyZXR1cm4gY29tcG9u ZW50X2FkZCgmcGRldi0+ZGV2LCAmdmM0X3ZlY19vcHMpOworfQorCitzdGF0aWMgaW50IHZjNF92 ZWNfZGV2X3JlbW92ZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQoreworCWNvbXBvbmVu dF9kZWwoJnBkZXYtPmRldiwgJnZjNF92ZWNfb3BzKTsKKwlyZXR1cm4gMDsKK30KKworc3RydWN0 IHBsYXRmb3JtX2RyaXZlciB2YzRfdmVjX2RyaXZlciA9IHsKKwkucHJvYmUgPSB2YzRfdmVjX2Rl dl9wcm9iZSwKKwkucmVtb3ZlID0gdmM0X3ZlY19kZXZfcmVtb3ZlLAorCS5kcml2ZXIgPSB7CisJ CS5uYW1lID0gInZjNF92ZWMiLAorCQkub2ZfbWF0Y2hfdGFibGUgPSB2YzRfdmVjX2R0X21hdGNo LAorCX0sCit9OwotLSAKMi4xMC4yCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVl ZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5m by9kcmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933480AbcK2Smv (ORCPT ); Tue, 29 Nov 2016 13:42:51 -0500 Received: from anholt.net ([50.246.234.109]:46160 "EHLO anholt.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932283AbcK2SmM (ORCPT ); Tue, 29 Nov 2016 13:42:12 -0500 From: Eric Anholt To: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org, Boris Brezillon , Eric Anholt Subject: [PATCH 3/6] drm/vc4: Add support for the VEC (Video Encoder) IP Date: Tue, 29 Nov 2016 10:41:59 -0800 Message-Id: <20161129184202.10640-4-eric@anholt.net> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20161129184202.10640-1-eric@anholt.net> References: <20161129184202.10640-1-eric@anholt.net> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Boris Brezillon The VEC IP is a TV DAC, providing support for PAL and NTSC standards. Signed-off-by: Boris Brezillon Signed-off-by: Eric Anholt --- drivers/gpu/drm/vc4/Makefile | 1 + drivers/gpu/drm/vc4/vc4_debugfs.c | 1 + drivers/gpu/drm/vc4/vc4_drv.c | 1 + drivers/gpu/drm/vc4/vc4_drv.h | 5 + drivers/gpu/drm/vc4/vc4_vec.c | 657 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 665 insertions(+) create mode 100644 drivers/gpu/drm/vc4/vc4_vec.c diff --git a/drivers/gpu/drm/vc4/Makefile b/drivers/gpu/drm/vc4/Makefile index fb77db755e0a..7757f69a8a77 100644 --- a/drivers/gpu/drm/vc4/Makefile +++ b/drivers/gpu/drm/vc4/Makefile @@ -11,6 +11,7 @@ vc4-y := \ vc4_kms.o \ vc4_gem.o \ vc4_hdmi.o \ + vc4_vec.o \ vc4_hvs.o \ vc4_irq.o \ vc4_plane.o \ diff --git a/drivers/gpu/drm/vc4/vc4_debugfs.c b/drivers/gpu/drm/vc4/vc4_debugfs.c index 245115d49c46..caf817bac885 100644 --- a/drivers/gpu/drm/vc4/vc4_debugfs.c +++ b/drivers/gpu/drm/vc4/vc4_debugfs.c @@ -19,6 +19,7 @@ static const struct drm_info_list vc4_debugfs_list[] = { {"bo_stats", vc4_bo_stats_debugfs, 0}, {"dpi_regs", vc4_dpi_debugfs_regs, 0}, {"hdmi_regs", vc4_hdmi_debugfs_regs, 0}, + {"vec_regs", vc4_vec_debugfs_regs, 0}, {"hvs_regs", vc4_hvs_debugfs_regs, 0}, {"crtc0_regs", vc4_crtc_debugfs_regs, 0, (void *)(uintptr_t)0}, {"crtc1_regs", vc4_crtc_debugfs_regs, 0, (void *)(uintptr_t)1}, diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c index 86aabf6d0f79..df3da26a849e 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.c +++ b/drivers/gpu/drm/vc4/vc4_drv.c @@ -294,6 +294,7 @@ static const struct component_master_ops vc4_drm_ops = { static struct platform_driver *const component_drivers[] = { &vc4_hdmi_driver, + &vc4_vec_driver, &vc4_dpi_driver, &vc4_hvs_driver, &vc4_crtc_driver, diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h index b6049cc25675..162821796bf3 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -17,6 +17,7 @@ struct vc4_dev { struct vc4_crtc *crtc[3]; struct vc4_v3d *v3d; struct vc4_dpi *dpi; + struct vc4_vec *vec; struct drm_fbdev_cma *fbdev; @@ -486,6 +487,10 @@ int vc4_queue_seqno_cb(struct drm_device *dev, extern struct platform_driver vc4_hdmi_driver; int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused); +/* vc4_hdmi.c */ +extern struct platform_driver vc4_vec_driver; +int vc4_vec_debugfs_regs(struct seq_file *m, void *unused); + /* vc4_irq.c */ irqreturn_t vc4_irq(int irq, void *arg); void vc4_irq_preinstall(struct drm_device *dev); diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c new file mode 100644 index 000000000000..32bb8ef985fb --- /dev/null +++ b/drivers/gpu/drm/vc4/vc4_vec.c @@ -0,0 +1,657 @@ +/* + * Copyright (C) 2016 Broadcom + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +/** + * DOC: VC4 SDTV module + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vc4_drv.h" +#include "vc4_regs.h" + +/* WSE Registers */ +#define VEC_WSE_RESET 0xc0 + +#define VEC_WSE_CONTROL 0xc4 +#define VEC_WSE_WSS_ENABLE BIT(7) + +#define VEC_WSE_WSS_DATA 0xc8 +#define VEC_WSE_VPS_DATA1 0xcc +#define VEC_WSE_VPS_CONTROL 0xd0 + +/* VEC Registers */ +#define VEC_REVID 0x100 + +#define VEC_CONFIG0 0x104 +#define VEC_CONFIG0_YDEL_MASK GENMASK(28, 26) +#define VEC_CONFIG0_YDEL(x) ((x) << 26) +#define VEC_CONFIG0_CDEL_MASK GENMASK(25, 24) +#define VEC_CONFIG0_CDEL(x) ((x) << 24) +#define VEC_CONFIG0_PBPR_FIL BIT(18) +#define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16) +#define VEC_CONFIG0_CHROMA_GAIN_UNITY (0 << 16) +#define VEC_CONFIG0_CHROMA_GAIN_1_32 (1 << 16) +#define VEC_CONFIG0_CHROMA_GAIN_1_16 (2 << 16) +#define VEC_CONFIG0_CHROMA_GAIN_1_8 (3 << 16) +#define VEC_CONFIG0_CBURST_GAIN_MASK GENMASK(14, 13) +#define VEC_CONFIG0_CBURST_GAIN_UNITY (0 << 13) +#define VEC_CONFIG0_CBURST_GAIN_1_128 (1 << 13) +#define VEC_CONFIG0_CBURST_GAIN_1_64 (2 << 13) +#define VEC_CONFIG0_CBURST_GAIN_1_32 (3 << 13) +#define VEC_CONFIG0_CHRBW1 BIT(11) +#define VEC_CONFIG0_CHRBW0 BIT(10) +#define VEC_CONFIG0_SYNCDIS BIT(9) +#define VEC_CONFIG0_BURDIS BIT(8) +#define VEC_CONFIG0_CHRDIS BIT(7) +#define VEC_CONFIG0_PDEN BIT(6) +#define VEC_CONFIG0_YCDELAY BIT(4) +#define VEC_CONFIG0_RAMPEN BIT(2) +#define VEC_CONFIG0_YCDIS BIT(2) +#define VEC_CONFIG0_STD_MASK GENMASK(1, 0) +#define VEC_CONFIG0_NTSC_STD 0 +#define VEC_CONFIG0_PAL_BDGHI_STD 1 +#define VEC_CONFIG0_PAL_N_STD 3 + +#define VEC_SCHPH 0x108 +#define VEC_SOFT_RESET 0x10c +#define VEC_CLMP0_START 0x144 +#define VEC_CLMP0_END 0x148 +#define VEC_FREQ3_2 0x180 +#define VEC_FREQ1_0 0x184 + +#define VEC_CONFIG1 0x188 +#define VEC_CONFIG_VEC_RESYNC_OFF BIT(18) +#define VEC_CONFIG_RGB219 BIT(17) +#define VEC_CONFIG_CBAR_EN BIT(16) +#define VEC_CONFIG_TC_OBB BIT(15) +#define VEC_CONFIG1_OUTPUT_MODE_MASK GENMASK(12, 10) +#define VEC_CONFIG1_C_Y_CVBS (0 << 10) +#define VEC_CONFIG1_CVBS_Y_C (1 << 10) +#define VEC_CONFIG1_PR_Y_PB (2 << 10) +#define VEC_CONFIG1_RGB (4 << 10) +#define VEC_CONFIG1_Y_C_CVBS (5 << 10) +#define VEC_CONFIG1_C_CVBS_Y (6 << 10) +#define VEC_CONFIG1_C_CVBS_CVBS (7 << 10) +#define VEC_CONFIG1_DIS_CHR BIT(9) +#define VEC_CONFIG1_DIS_LUMA BIT(8) +#define VEC_CONFIG1_YCBCR_IN BIT(6) +#define VEC_CONFIG1_DITHER_TYPE_LFSR 0 +#define VEC_CONFIG1_DITHER_TYPE_COUNTER BIT(5) +#define VEC_CONFIG1_DITHER_EN BIT(4) +#define VEC_CONFIG1_CYDELAY BIT(3) +#define VEC_CONFIG1_LUMADIS BIT(2) +#define VEC_CONFIG1_COMPDIS BIT(1) +#define VEC_CONFIG1_CUSTOM_FREQ BIT(0) + +#define VEC_CONFIG2 0x18c +#define VEC_CONFIG2_PROG_SCAN BIT(15) +#define VEC_CONFIG2_SYNC_ADJ_MASK GENMASK(14, 12) +#define VEC_CONFIG2_SYNC_ADJ(x) (((x) / 2) << 12) +#define VEC_CONFIG2_PBPR_EN BIT(10) +#define VEC_CONFIG2_UV_DIG_DIS BIT(6) +#define VEC_CONFIG2_RGB_DIG_DIS BIT(5) +#define VEC_CONFIG2_TMUX_MASK GENMASK(3, 2) +#define VEC_CONFIG2_TMUX_DRIVE0 (0 << 2) +#define VEC_CONFIG2_TMUX_RG_COMP (1 << 2) +#define VEC_CONFIG2_TMUX_UV_YC (2 << 2) +#define VEC_CONFIG2_TMUX_SYNC_YC (3 << 2) + +#define VEC_INTERRUPT_CONTROL 0x190 +#define VEC_INTERRUPT_STATUS 0x194 +#define VEC_FCW_SECAM_B 0x198 +#define VEC_SECAM_GAIN_VAL 0x19c + +#define VEC_CONFIG3 0x1a0 +#define VEC_CONFIG3_HORIZ_LEN_STD (0 << 0) +#define VEC_CONFIG3_HORIZ_LEN_MPEG1_SIF (1 << 0) +#define VEC_CONFIG3_SHAPE_NON_LINEAR BIT(1) + +#define VEC_STATUS0 0x200 +#define VEC_MASK0 0x204 + +#define VEC_CFG 0x208 +#define VEC_CFG_SG_MODE_MASK GENMASK(6, 5) +#define VEC_CFG_SG_MODE(x) ((x) << 5) +#define VEC_CFG_SG_EN BIT(4) +#define VEC_CFG_VEC_EN BIT(3) +#define VEC_CFG_MB_EN BIT(2) +#define VEC_CFG_ENABLE BIT(1) +#define VEC_CFG_TB_EN BIT(0) + +#define VEC_DAC_TEST 0x20c + +#define VEC_DAC_CONFIG 0x210 +#define VEC_DAC_CONFIG_LDO_BIAS_CTRL(x) ((x) << 24) +#define VEC_DAC_CONFIG_DRIVER_CTRL(x) ((x) << 16) +#define VEC_DAC_CONFIG_DAC_CTRL(x) (x) + +#define VEC_DAC_MISC 0x214 +#define VEC_DAC_MISC_VCD_CTRL_MASK GENMASK(31, 16) +#define VEC_DAC_MISC_VCD_CTRL(x) ((x) << 16) +#define VEC_DAC_MISC_VID_ACT BIT(8) +#define VEC_DAC_MISC_VCD_PWRDN BIT(6) +#define VEC_DAC_MISC_BIAS_PWRDN BIT(5) +#define VEC_DAC_MISC_DAC_PWRDN BIT(2) +#define VEC_DAC_MISC_LDO_PWRDN BIT(1) +#define VEC_DAC_MISC_DAC_RST_N BIT(0) + + +/* General VEC hardware state. */ +struct vc4_vec { + struct platform_device *pdev; + + struct drm_encoder *encoder; + struct drm_connector *connector; + + void __iomem *regs; + + struct clk *clock; + + const struct vc4_vec_tv_mode *tv_mode; +}; + +#define VEC_READ(offset) readl(vec->regs + (offset)) +#define VEC_WRITE(offset, val) writel(val, vec->regs + (offset)) + +/* VC4 VEC encoder KMS struct */ +struct vc4_vec_encoder { + struct vc4_encoder base; + struct vc4_vec *vec; +}; + +static inline struct vc4_vec_encoder * +to_vc4_vec_encoder(struct drm_encoder *encoder) +{ + return container_of(encoder, struct vc4_vec_encoder, base.base); +} + +/* VC4 VEC connector KMS struct */ +struct vc4_vec_connector { + struct drm_connector base; + struct vc4_vec *vec; + + /* Since the connector is attached to just the one encoder, + * this is the reference to it so we can do the best_encoder() + * hook. + */ + struct drm_encoder *encoder; +}; + +static inline struct vc4_vec_connector * +to_vc4_vec_connector(struct drm_connector *connector) +{ + return container_of(connector, struct vc4_vec_connector, base); +} + +enum vc4_vec_tv_mode_id { + VC4_VEC_TV_MODE_NTSC, + VC4_VEC_TV_MODE_NTSC_J, + VC4_VEC_TV_MODE_PAL, + VC4_VEC_TV_MODE_PAL_M, +}; + +struct vc4_vec_tv_mode { + const struct drm_display_mode *mode; + void (*mode_set)(struct vc4_vec *vec); +}; + +#define VEC_REG(reg) { reg, #reg } +static const struct { + u32 reg; + const char *name; +} vec_regs[] = { + VEC_REG(VEC_WSE_CONTROL), + VEC_REG(VEC_WSE_WSS_DATA), + VEC_REG(VEC_WSE_VPS_DATA1), + VEC_REG(VEC_WSE_VPS_CONTROL), + VEC_REG(VEC_REVID), + VEC_REG(VEC_CONFIG0), + VEC_REG(VEC_SCHPH), + VEC_REG(VEC_CLMP0_START), + VEC_REG(VEC_CLMP0_END), + VEC_REG(VEC_FREQ3_2), + VEC_REG(VEC_FREQ1_0), + VEC_REG(VEC_CONFIG1), + VEC_REG(VEC_CONFIG2), + VEC_REG(VEC_INTERRUPT_CONTROL), + VEC_REG(VEC_INTERRUPT_STATUS), + VEC_REG(VEC_FCW_SECAM_B), + VEC_REG(VEC_SECAM_GAIN_VAL), + VEC_REG(VEC_CONFIG3), + VEC_REG(VEC_STATUS0), + VEC_REG(VEC_MASK0), + VEC_REG(VEC_CFG), + VEC_REG(VEC_DAC_TEST), + VEC_REG(VEC_DAC_CONFIG), + VEC_REG(VEC_DAC_MISC), +}; + +#ifdef CONFIG_DEBUG_FS +int vc4_vec_debugfs_regs(struct seq_file *m, void *unused) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + struct vc4_vec *vec = vc4->vec; + int i; + + if (!vec) + return 0; + + for (i = 0; i < ARRAY_SIZE(vec_regs); i++) { + seq_printf(m, "%s (0x%04x): 0x%08x\n", + vec_regs[i].name, vec_regs[i].reg, + VEC_READ(vec_regs[i].reg)); + } + + return 0; +} +#endif + +static void vc4_vec_ntsc_mode_set(struct vc4_vec *vec) +{ + VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN); + VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS); +} + +static void vc4_vec_ntsc_j_mode_set(struct vc4_vec *vec) +{ + VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_NTSC_STD); + VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS); +} + +static const struct drm_display_mode ntsc_mode = { + DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 13500, + 720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0, + 480, 480 + 3, 480 + 3 + 3, 480 + 3 + 3 + 16, 0, + DRM_MODE_FLAG_INTERLACE) +}; + +static void vc4_vec_pal_mode_set(struct vc4_vec *vec) +{ + VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_PAL_BDGHI_STD); + VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS); +} + +static void vc4_vec_pal_m_mode_set(struct vc4_vec *vec) +{ + VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_PAL_BDGHI_STD); + VEC_WRITE(VEC_CONFIG1, + VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ); + VEC_WRITE(VEC_FREQ3_2, 0x223b); + VEC_WRITE(VEC_FREQ1_0, 0x61d1); +} + +static const struct drm_display_mode pal_mode = { + DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 13500, + 720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0, + 576, 576 + 2, 576 + 2 + 3, 576 + 2 + 3 + 20, 0, + DRM_MODE_FLAG_INTERLACE) +}; + +static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = { + [VC4_VEC_TV_MODE_NTSC] = { + .mode = &ntsc_mode, + .mode_set = vc4_vec_ntsc_mode_set, + }, + [VC4_VEC_TV_MODE_NTSC_J] = { + .mode = &ntsc_mode, + .mode_set = vc4_vec_ntsc_j_mode_set, + }, + [VC4_VEC_TV_MODE_PAL] = { + .mode = &pal_mode, + .mode_set = vc4_vec_pal_mode_set, + }, + [VC4_VEC_TV_MODE_PAL_M] = { + .mode = &pal_mode, + .mode_set = vc4_vec_pal_m_mode_set, + }, +}; + +static enum drm_connector_status +vc4_vec_connector_detect(struct drm_connector *connector, bool force) +{ + return connector_status_unknown; +} + +static void vc4_vec_connector_destroy(struct drm_connector *connector) +{ + drm_connector_unregister(connector); + drm_connector_cleanup(connector); +} + +static int vc4_vec_connector_get_modes(struct drm_connector *connector) +{ + struct drm_connector_state *state = connector->state; + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(connector->dev, + vc4_vec_tv_modes[state->tv.mode].mode); + if (!mode) { + DRM_ERROR("Failed to create a new display mode\n"); + return -ENOMEM; + } + + drm_mode_probed_add(connector, mode); + + return 1; +} + +static const struct drm_connector_funcs vc4_vec_connector_funcs = { + .dpms = drm_atomic_helper_connector_dpms, + .detect = vc4_vec_connector_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .set_property = drm_atomic_helper_connector_set_property, + .destroy = vc4_vec_connector_destroy, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static const struct drm_connector_helper_funcs vc4_vec_connector_helper_funcs = { + .get_modes = vc4_vec_connector_get_modes, +}; + +static struct drm_connector *vc4_vec_connector_init(struct drm_device *dev, + struct vc4_vec *vec) +{ + struct drm_connector *connector = NULL; + struct vc4_vec_connector *vec_connector; + + vec_connector = devm_kzalloc(dev->dev, sizeof(*vec_connector), + GFP_KERNEL); + if (!vec_connector) + return ERR_PTR(-ENOMEM); + + connector = &vec_connector->base; + connector->interlace_allowed = true; + + vec_connector->encoder = vec->encoder; + vec_connector->vec = vec; + + drm_connector_init(dev, connector, &vc4_vec_connector_funcs, + DRM_MODE_CONNECTOR_Composite); + drm_connector_helper_add(connector, &vc4_vec_connector_helper_funcs); + + drm_object_attach_property(&connector->base, + dev->mode_config.tv_mode_property, + VC4_VEC_TV_MODE_NTSC); + vec->tv_mode = &vc4_vec_tv_modes[VC4_VEC_TV_MODE_NTSC]; + + drm_mode_connector_attach_encoder(connector, vec->encoder); + + return connector; +} + +static const struct drm_encoder_funcs vc4_vec_encoder_funcs = { + .destroy = drm_encoder_cleanup, +}; + +static void vc4_vec_encoder_disable(struct drm_encoder *encoder) +{ + struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder); + struct vc4_vec *vec = vc4_vec_encoder->vec; + int ret; + + VEC_WRITE(VEC_CFG, 0); + VEC_WRITE(VEC_DAC_MISC, + VEC_DAC_MISC_VCD_PWRDN | + VEC_DAC_MISC_BIAS_PWRDN | + VEC_DAC_MISC_DAC_PWRDN | + VEC_DAC_MISC_LDO_PWRDN); + + clk_disable_unprepare(vec->clock); + + ret = pm_runtime_put(&vec->pdev->dev); + if (ret < 0) { + DRM_ERROR("Failed to release power domain: %d\n", ret); + return; + } +} + +static void vc4_vec_encoder_enable(struct drm_encoder *encoder) +{ + struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder); + struct vc4_vec *vec = vc4_vec_encoder->vec; + int ret; + + ret = pm_runtime_get_sync(&vec->pdev->dev); + if (ret < 0) { + DRM_ERROR("Failed to retain power domain: %d\n", ret); + return; + } + + /* + * We need to set the clock rate each time we enable the encoder + * because there's a chance we share the same parent with the HDMI + * clock, and both drivers are requesting different rates. + * The good news is, these 2 encoders cannot be enabled at the same + * time, thus preventing incompatible rate requests. + */ + ret = clk_set_rate(vec->clock, 108000000); + if (ret) { + DRM_ERROR("Failed to set clock rate: %d\n", ret); + return; + } + + ret = clk_prepare_enable(vec->clock); + if (ret) { + DRM_ERROR("Failed to turn on core clock: %d\n", ret); + return; + } + + /* Reset the different blocks */ + VEC_WRITE(VEC_WSE_RESET, 1); + VEC_WRITE(VEC_SOFT_RESET, 1); + + /* Disable the CGSM-A and WSE blocks */ + VEC_WRITE(VEC_WSE_CONTROL, 0); + + /* Write config common to all modes. */ + + /* + * Color subcarrier phase: phase = 360 * SCHPH / 256. + * 0x28 <=> 39.375 deg. + */ + VEC_WRITE(VEC_SCHPH, 0x28); + + /* + * Reset to default values. + */ + VEC_WRITE(VEC_CLMP0_START, 0xac); + VEC_WRITE(VEC_CLMP0_END, 0xec); + VEC_WRITE(VEC_CONFIG2, + VEC_CONFIG2_UV_DIG_DIS | VEC_CONFIG2_RGB_DIG_DIS); + VEC_WRITE(VEC_CONFIG3, VEC_CONFIG3_HORIZ_LEN_STD); + VEC_WRITE(VEC_DAC_CONFIG, + VEC_DAC_CONFIG_DAC_CTRL(0xc) | + VEC_DAC_CONFIG_DRIVER_CTRL(0xc) | + VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x46)); + + /* Mask all interrupts. */ + VEC_WRITE(VEC_MASK0, 0); + + vec->tv_mode->mode_set(vec); + + VEC_WRITE(VEC_DAC_MISC, + VEC_DAC_MISC_VID_ACT | VEC_DAC_MISC_DAC_RST_N); + VEC_WRITE(VEC_CFG, VEC_CFG_VEC_EN); +} + + +static bool vc4_vec_encoder_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + return true; +} + +static void vc4_vec_encoder_atomic_mode_set(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder); + struct vc4_vec *vec = vc4_vec_encoder->vec; + + vec->tv_mode = &vc4_vec_tv_modes[conn_state->tv.mode]; +} + +static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + const struct vc4_vec_tv_mode *vec_mode; + + vec_mode = &vc4_vec_tv_modes[conn_state->tv.mode]; + + if (conn_state->crtc && + !drm_mode_equal(vec_mode->mode, &crtc_state->adjusted_mode)) + return -EINVAL; + + return 0; +} + +static const struct drm_encoder_helper_funcs vc4_vec_encoder_helper_funcs = { + .disable = vc4_vec_encoder_disable, + .enable = vc4_vec_encoder_enable, + .mode_fixup = vc4_vec_encoder_mode_fixup, + .atomic_check = vc4_vec_encoder_atomic_check, + .atomic_mode_set = vc4_vec_encoder_atomic_mode_set, +}; + +static const struct of_device_id vc4_vec_dt_match[] = { + { .compatible = "brcm,bcm2835-vec", .data = NULL }, + { /* sentinel */ }, +}; + +static const char * const tv_mode_names[] = { + [VC4_VEC_TV_MODE_NTSC] = "NTSC", + [VC4_VEC_TV_MODE_NTSC_J] = "NTSC-J", + [VC4_VEC_TV_MODE_PAL] = "PAL", + [VC4_VEC_TV_MODE_PAL_M] = "PAL-M", +}; + +static int vc4_vec_bind(struct device *dev, struct device *master, void *data) +{ + struct platform_device *pdev = to_platform_device(dev); + struct drm_device *drm = dev_get_drvdata(master); + struct vc4_dev *vc4 = to_vc4_dev(drm); + struct vc4_vec *vec; + struct vc4_vec_encoder *vc4_vec_encoder; + int ret; + + ret = drm_mode_create_tv_properties(drm, ARRAY_SIZE(tv_mode_names), + tv_mode_names); + if (ret) + return ret; + + vec = devm_kzalloc(dev, sizeof(*vec), GFP_KERNEL); + if (!vec) + return -ENOMEM; + + vc4_vec_encoder = devm_kzalloc(dev, sizeof(*vc4_vec_encoder), + GFP_KERNEL); + if (!vc4_vec_encoder) + return -ENOMEM; + vc4_vec_encoder->base.type = VC4_ENCODER_TYPE_VEC; + vc4_vec_encoder->vec = vec; + vec->encoder = &vc4_vec_encoder->base.base; + + vec->pdev = pdev; + vec->regs = vc4_ioremap_regs(pdev, 0); + if (IS_ERR(vec->regs)) + return PTR_ERR(vec->regs); + + vec->clock = devm_clk_get(dev, NULL); + if (IS_ERR(vec->clock)) { + ret = PTR_ERR(vec->clock); + if (ret != -EPROBE_DEFER) + DRM_ERROR("Failed to get clock: %d\n", ret); + return ret; + } + + pm_runtime_enable(dev); + + drm_encoder_init(drm, vec->encoder, &vc4_vec_encoder_funcs, + DRM_MODE_ENCODER_TVDAC, NULL); + drm_encoder_helper_add(vec->encoder, &vc4_vec_encoder_helper_funcs); + + vec->connector = vc4_vec_connector_init(drm, vec); + if (IS_ERR(vec->connector)) { + ret = PTR_ERR(vec->connector); + goto err_destroy_encoder; + } + + dev_set_drvdata(dev, vec); + + vc4->vec = vec; + + return 0; + +err_destroy_encoder: + drm_encoder_cleanup(vec->encoder); + pm_runtime_disable(dev); + + return ret; +} + +static void vc4_vec_unbind(struct device *dev, struct device *master, + void *data) +{ + struct drm_device *drm = dev_get_drvdata(master); + struct vc4_dev *vc4 = to_vc4_dev(drm); + struct vc4_vec *vec = dev_get_drvdata(dev); + + vc4_vec_connector_destroy(vec->connector); + drm_encoder_cleanup(vec->encoder); + pm_runtime_disable(dev); + + vc4->vec = NULL; +} + +static const struct component_ops vc4_vec_ops = { + .bind = vc4_vec_bind, + .unbind = vc4_vec_unbind, +}; + +static int vc4_vec_dev_probe(struct platform_device *pdev) +{ + return component_add(&pdev->dev, &vc4_vec_ops); +} + +static int vc4_vec_dev_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &vc4_vec_ops); + return 0; +} + +struct platform_driver vc4_vec_driver = { + .probe = vc4_vec_dev_probe, + .remove = vc4_vec_dev_remove, + .driver = { + .name = "vc4_vec", + .of_match_table = vc4_vec_dt_match, + }, +}; -- 2.10.2