From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v2] drm/i915/dsi: Do not clear DPOUNIT_CLOCK_GATE_DISABLE from vlv_init_display_clock_gating Date: Mon, 5 Dec 2016 20:52:01 +0200 Message-ID: <20161205185201.GH31595@intel.com> References: <20161202142904.25613-1-hdegoede@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <20161202142904.25613-1-hdegoede@redhat.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Hans de Goede Cc: Daniel Vetter , intel-gfx , stable@vger.kernel.org, dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org T24gRnJpLCBEZWMgMDIsIDIwMTYgYXQgMDM6Mjk6MDRQTSArMDEwMCwgSGFucyBkZSBHb2VkZSB3 cm90ZToKPiBPbiBteSBDaGVycnl0cmFpbCBDVUJFIGl3b3JrOCBBaXIgdGFibGV0IFBJUEUtQSB3 b3VsZCBnZXQgc3R1Y2sgb24gbG9hZGluZwo+IGk5MTUgYXQgYm9vdCAxIG91dCBvZiBldmVyeSAz IGJvb3RzLCByZXN1bHRpbmcgaW4gYSBub24gZnVuY3Rpb25hbCBMQ0QuCj4gT25jZSB0aGUgaTkx NSBkcml2ZXIgaGFzIHN1Y2Nlc3NmdWxseSBsb2FkZWQsIHRoZSBwYW5lbCBjYW4gYmUgZGlzYWJs ZWQgLwo+IGVuYWJsZWQgd2l0aG91dCBoaXR0aW5nIHRoaXMgaXNzdWUuCj4gCj4gVGhlIGdldHRp bmcgc3R1Y2sgaXMgY2F1c2VkIGJ5IHZsdl9pbml0X2Rpc3BsYXlfY2xvY2tfZ2F0aW5nKCkgY2xl YXJpbmcKPiB0aGUgRFBPVU5JVF9DTE9DS19HQVRFX0RJU0FCTEUgYml0IGluIERTUENMS19HQVRF X0Qgd2hlbiBjYWxsZWQgZnJvbQo+IGNodl9waXBlX3Bvd2VyX3dlbGxfb3BzLmVuYWJsZSgpIG9u IGRyaXZlciBsb2FkLCB3aGlsZSBhIHBpcGUgaXMgZW5hYmxlZAo+IGRyaXZpbmcgdGhlIERTSSBM Q0QgYnkgdGhlIEJJT1MuCj4gCj4gQ2xlYXJpbmcgdGhpcyBiaXQgd2hpbGUgRFNJIGlzIGluIHVz ZSBpcyBhIGtub3duIGlzc3VlIGFuZAo+IGludGVsX2RzaV9wcmVfZW5hYmxlKCkgLyBpbnRlbF9k c2lfcG9zdF9kaXNhYmxlKCkgYWxyZWFkeSBzZXQgLyBjbGVhciBpdAo+IGFzIGFwcHJvcHJpYXRl Lgo+IAo+IFRoaXMgY29tbWl0IG1vZGlmaWVzIHZsdl9pbml0X2Rpc3BsYXlfY2xvY2tfZ2F0aW5n KCkgdG8gbGVhdmUgdGhlCj4gRFBPVU5JVF9DTE9DS19HQVRFX0RJU0FCTEUgYml0IGFsb25lIGZp eGluZyB0aGUgcGlwZSBnZXR0aW5nIHN0dWNrLgo+IAo+IEJ1Z0xpbms6IGh0dHBzOi8vYnVncy5m cmVlZGVza3RvcC5vcmcvc2hvd19idWcuY2dpP2lkPTk3MzMwCj4gQ2M6IHN0YWJsZUB2Z2VyLmtl cm5lbC5vcmcKPiBTaWduZWQtb2ZmLWJ5OiBIYW5zIGRlIEdvZWRlIDxoZGVnb2VkZUByZWRoYXQu Y29tPgo+IFJldmlld2VkLWJ5OiBWaWxsZSBTeXJqw6Rsw6QgPHZpbGxlLnN5cmphbGFAbGludXgu aW50ZWwuY29tPgo+IC0tLQo+IENoYW5nZXMgaW4gdjI6Cj4gLVJlcGxhY2UgUElQRS1BIHdpdGgg ImEgcGlwZSIgb3IgInRoZSBwaXBlIiBpbiB0aGUgY29tbWl0IG1zZyBhbmQgY29tbWVudAoKUHVz aGVkIHRvIGRpbnEgd2l0aCBzL0J1Z0xpbmsvQnVnemlsbGEvIGFuZCBjaGFuZ2Vsb2cgbW92ZWQg aW50byB0aGUKY29tbWl0IG1lc3NhZ2UgcHJvcGVyLiBUaGFua3MgZm9yIHRoZSBwYXRjaC4KCj4g LS0tCj4gIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX3J1bnRpbWVfcG0uYyB8IDEzICsrKysr KysrKysrKy0KPiAgMSBmaWxlIGNoYW5nZWQsIDEyIGluc2VydGlvbnMoKyksIDEgZGVsZXRpb24o LSkKPiAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfcnVudGltZV9w bS5jIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfcnVudGltZV9wbS5jCj4gaW5kZXggMzU2 YzY2Mi4uODdiNGFmMCAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9y dW50aW1lX3BtLmMKPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9ydW50aW1lX3Bt LmMKPiBAQCAtMTAzOSw3ICsxMDM5LDE4IEBAIHN0YXRpYyBib29sIHZsdl9wb3dlcl93ZWxsX2Vu YWJsZWQoc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2LAo+ICAKPiAgc3RhdGljIHZv aWQgdmx2X2luaXRfZGlzcGxheV9jbG9ja19nYXRpbmcoc3RydWN0IGRybV9pOTE1X3ByaXZhdGUg KmRldl9wcml2KQo+ICB7Cj4gLQlJOTE1X1dSSVRFKERTUENMS19HQVRFX0QsIFZSSFVOSVRfQ0xP Q0tfR0FURV9ESVNBQkxFKTsKPiArCXUzMiB2YWw7Cj4gKwo+ICsJLyoKPiArCSAqIE9uIGRyaXZl ciBsb2FkLCBhIHBpcGUgbWF5IGJlIGFjdGl2ZSBhbmQgZHJpdmluZyBhIERTSSBkaXNwbGF5Lgo+ ICsJICogUHJlc2VydmUgRFBPVU5JVF9DTE9DS19HQVRFX0RJU0FCTEUgdG8gYXZvaWQgdGhlIHBp cGUgZ2V0dGluZyBzdHVjawo+ICsJICogKGFuZCBuZXZlciByZWNvdmVyaW5nKSBpbiB0aGlzIGNh c2UuIGludGVsX2RzaV9wb3N0X2Rpc2FibGUoKSB3aWxsCj4gKwkgKiBjbGVhciBpdCB3aGVuIHdl IHR1cm4gb2ZmIHRoZSBkaXNwbGF5Lgo+ICsJICovCj4gKwl2YWwgPSBJOTE1X1JFQUQoRFNQQ0xL X0dBVEVfRCk7Cj4gKwl2YWwgJj0gRFBPVU5JVF9DTE9DS19HQVRFX0RJU0FCTEU7Cj4gKwl2YWwg fD0gVlJIVU5JVF9DTE9DS19HQVRFX0RJU0FCTEU7Cj4gKwlJOTE1X1dSSVRFKERTUENMS19HQVRF X0QsIHZhbCk7Cj4gIAo+ICAJLyoKPiAgCSAqIERpc2FibGUgdHJpY2tsZSBmZWVkIGFuZCBlbmFi bGUgcG5kIGRlYWRsaW5lIGNhbGN1bGF0aW9uCj4gLS0gCj4gMi45LjMKCi0tIApWaWxsZSBTeXJq w6Rsw6QKSW50ZWwgT1RDCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9w Lm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1k ZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com ([134.134.136.31]:30345 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751895AbcLESwH (ORCPT ); Mon, 5 Dec 2016 13:52:07 -0500 Date: Mon, 5 Dec 2016 20:52:01 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Hans de Goede Cc: Daniel Vetter , Jani Nikula , intel-gfx , dri-devel@lists.freedesktop.org, stable@vger.kernel.org Subject: Re: [PATCH v2] drm/i915/dsi: Do not clear DPOUNIT_CLOCK_GATE_DISABLE from vlv_init_display_clock_gating Message-ID: <20161205185201.GH31595@intel.com> References: <20161202142904.25613-1-hdegoede@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20161202142904.25613-1-hdegoede@redhat.com> Sender: stable-owner@vger.kernel.org List-ID: On Fri, Dec 02, 2016 at 03:29:04PM +0100, Hans de Goede wrote: > On my Cherrytrail CUBE iwork8 Air tablet PIPE-A would get stuck on loading > i915 at boot 1 out of every 3 boots, resulting in a non functional LCD. > Once the i915 driver has successfully loaded, the panel can be disabled / > enabled without hitting this issue. > > The getting stuck is caused by vlv_init_display_clock_gating() clearing > the DPOUNIT_CLOCK_GATE_DISABLE bit in DSPCLK_GATE_D when called from > chv_pipe_power_well_ops.enable() on driver load, while a pipe is enabled > driving the DSI LCD by the BIOS. > > Clearing this bit while DSI is in use is a known issue and > intel_dsi_pre_enable() / intel_dsi_post_disable() already set / clear it > as appropriate. > > This commit modifies vlv_init_display_clock_gating() to leave the > DPOUNIT_CLOCK_GATE_DISABLE bit alone fixing the pipe getting stuck. > > BugLink: https://bugs.freedesktop.org/show_bug.cgi?id=97330 > Cc: stable@vger.kernel.org > Signed-off-by: Hans de Goede > Reviewed-by: Ville Syrj�l� > --- > Changes in v2: > -Replace PIPE-A with "a pipe" or "the pipe" in the commit msg and comment Pushed to dinq with s/BugLink/Bugzilla/ and changelog moved into the commit message proper. Thanks for the patch. > --- > drivers/gpu/drm/i915/intel_runtime_pm.c | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > index 356c662..87b4af0 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -1039,7 +1039,18 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, > > static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) > { > - I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); > + u32 val; > + > + /* > + * On driver load, a pipe may be active and driving a DSI display. > + * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck > + * (and never recovering) in this case. intel_dsi_post_disable() will > + * clear it when we turn off the display. > + */ > + val = I915_READ(DSPCLK_GATE_D); > + val &= DPOUNIT_CLOCK_GATE_DISABLE; > + val |= VRHUNIT_CLOCK_GATE_DISABLE; > + I915_WRITE(DSPCLK_GATE_D, val); > > /* > * Disable trickle feed and enable pnd deadline calculation > -- > 2.9.3 -- Ville Syrj�l� Intel OTC