From: David Gibson <david@gibson.dropbear.id.au>
To: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Cc: qemu-ppc@nongnu.org, rth@twiddle.net, qemu-devel@nongnu.org,
bharata@linux.vnet.ibm.com
Subject: Re: [Qemu-devel] [PATCH 13/13] target-ppc: Add xxperm and xxpermr instructions
Date: Tue, 6 Dec 2016 15:11:22 +1100 [thread overview]
Message-ID: <20161206041122.GP32366@umbus.fritz.box> (raw)
In-Reply-To: <1480937130-24561-14-git-send-email-nikunj@linux.vnet.ibm.com>
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On Mon, Dec 05, 2016 at 04:55:30PM +0530, Nikunj A Dadhania wrote:
> From: Bharata B Rao <bharata@linux.vnet.ibm.com>
>
> xxperm: VSX Vector Permute
> xxpermr: VSX Vector Permute Right-indexed
>
> Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
> target-ppc/fpu_helper.c | 50 +++++++++++++++++++++++++++++++++++++
> target-ppc/helper.h | 2 ++
> target-ppc/translate/vsx-impl.inc.c | 2 ++
> target-ppc/translate/vsx-ops.inc.c | 2 ++
> 4 files changed, 56 insertions(+)
>
> diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
> index 3b867cf..be552c7 100644
> --- a/target-ppc/fpu_helper.c
> +++ b/target-ppc/fpu_helper.c
> @@ -2869,3 +2869,53 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
> float_check_status(env);
> return xt;
> }
> +
> +static void vsr_copy_256(ppc_vsr_t *xa, ppc_vsr_t *xt, int8_t *src)
> +{
> +#if defined(HOST_WORDS_BIGENDIAN)
> + memcpy(src, xa, sizeof(*xa));
> + memcpy(src + 16, xt, sizeof(*xt));
> +#else
> + memcpy(src, xt, sizeof(*xt));
> + memcpy(src + 16, xa, sizeof(*xa));
Is this right? I thought the order of the bytes within each word
varied with the host endianness as well.
> +#endif
> +}
> +
> +static int8_t vsr_get_byte(int8_t *src, int bound, int idx)
> +{
> + if (idx >= bound) {
> + return 0xFF;
> + }
AFAICT you don't need this check. For both xxperm and xxpermr you're
already masking the index to 5 bits, so it can't exceed 31.
> +#if defined(HOST_WORDS_BIGENDIAN)
> + return src[idx];
> +#else
> + return src[bound - 1 - idx];
> +#endif
> +}
> +
> +#define VSX_XXPERM(op, indexed) \
> +void helper_##op(CPUPPCState *env, uint32_t opcode) \
> +{ \
> + ppc_vsr_t xt, xa, pcv; \
> + int i, idx; \
> + int8_t src[32]; \
> + \
> + getVSR(xA(opcode), &xa, env); \
> + getVSR(xT(opcode), &xt, env); \
> + getVSR(xB(opcode), &pcv, env); \
> + \
> + vsr_copy_256(&xa, &xt, src); \
You have a double copy here AFAICT - first from the actual env
structure to xt and xa, then to the src array. That seems like it
would be good to avoid.
It seems like it would nice in any case to avoid even the one copy.
You'd need a temporary for the output of course and to copy that, but
you should be able to combine indexed with host endianness to
translate each index to retrieve directly from the VSR values in env.
> + for (i = 0; i < 16; i++) { \
> + idx = pcv.VsrB(i) & 0x1F; \
> + if (indexed) { \
> + xt.VsrB(i) = vsr_get_byte(src, 32, 31 - idx); \
> + } else { \
> + xt.VsrB(i) = vsr_get_byte(src, 32, idx); \
> + } \
> + } \
> + putVSR(xT(opcode), &xt, env); \
> +}
> +
> +VSX_XXPERM(xxperm, 0)
> +VSX_XXPERM(xxpermr, 1)
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 9f812c8..399cf99 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -538,6 +538,8 @@ DEF_HELPER_2(xvrspip, void, env, i32)
> DEF_HELPER_2(xvrspiz, void, env, i32)
> DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
> DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32)
> +DEF_HELPER_2(xxperm, void, env, i32)
> +DEF_HELPER_2(xxpermr, void, env, i32)
>
> DEF_HELPER_2(efscfsi, i32, env, i32)
> DEF_HELPER_2(efscfui, i32, env, i32)
> diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
> index 77f098b..2ad152e 100644
> --- a/target-ppc/translate/vsx-impl.inc.c
> +++ b/target-ppc/translate/vsx-impl.inc.c
> @@ -914,6 +914,8 @@ GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
> GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
> GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
> GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
> +GEN_VSX_HELPER_2(xxperm, 0x08, 0x03, 0, PPC2_ISA300)
> +GEN_VSX_HELPER_2(xxpermr, 0x08, 0x07, 0, PPC2_ISA300)
>
> static void gen_xxbrd(DisasContext *ctx)
> {
> diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
> index 42e83d2..93fb9b8 100644
> --- a/target-ppc/translate/vsx-ops.inc.c
> +++ b/target-ppc/translate/vsx-ops.inc.c
> @@ -275,6 +275,8 @@ VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
> VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
> GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
> GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
> +GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300),
> +GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
> GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
> GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
> GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2016-12-06 4:12 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-05 11:25 [Qemu-devel] [PATCH ppc-for-2.9 00/13] POWER9 TCG enablements - part9 Nikunj A Dadhania
2016-12-05 11:25 ` [Qemu-devel] [PATCH 01/13] target-ppc: move ppc_vsr_t to common header Nikunj A Dadhania
2016-12-05 11:25 ` [Qemu-devel] [PATCH 02/13] target-ppc: add mask_u128 routine Nikunj A Dadhania
2016-12-05 17:36 ` Richard Henderson
2016-12-06 5:19 ` Nikunj A Dadhania
2016-12-05 11:25 ` [Qemu-devel] [PATCH 03/13] target-ppc: implement lxvl instruction Nikunj A Dadhania
2016-12-05 17:46 ` Richard Henderson
2016-12-06 5:25 ` Nikunj A Dadhania
2016-12-06 10:11 ` Nikunj A Dadhania
2016-12-05 11:25 ` [Qemu-devel] [PATCH 04/13] target-ppc: implement lxvll instruction Nikunj A Dadhania
2016-12-05 17:52 ` Richard Henderson
2016-12-05 17:59 ` Richard Henderson
2016-12-06 5:45 ` Nikunj A Dadhania
2016-12-05 11:25 ` [Qemu-devel] [PATCH 05/13] target-ppc: implement stxvl instruction Nikunj A Dadhania
2016-12-05 17:55 ` Richard Henderson
2016-12-06 5:46 ` Nikunj A Dadhania
2016-12-05 11:25 ` [Qemu-devel] [PATCH 06/13] target-ppc: implement stxvll instructions Nikunj A Dadhania
2016-12-05 17:57 ` Richard Henderson
2016-12-06 6:03 ` Nikunj A Dadhania
2016-12-05 11:25 ` [Qemu-devel] [PATCH 07/13] target-ppc: implement xxextractuw instruction Nikunj A Dadhania
2016-12-05 18:10 ` Richard Henderson
2016-12-05 11:25 ` [Qemu-devel] [PATCH 08/13] target-ppc: implement xxinsertw instruction Nikunj A Dadhania
2016-12-05 18:14 ` Richard Henderson
2016-12-05 11:25 ` [Qemu-devel] [PATCH 09/13] target-ppc: implement stop instruction Nikunj A Dadhania
2016-12-05 11:25 ` [Qemu-devel] [PATCH 10/13] target-ppc: implement xsabsqp/xsnabsqp instruction Nikunj A Dadhania
2016-12-05 18:14 ` Richard Henderson
2016-12-05 11:25 ` [Qemu-devel] [PATCH 11/13] target-ppc: implement xsnegqp instruction Nikunj A Dadhania
2016-12-05 18:15 ` Richard Henderson
2016-12-06 8:45 ` Nikunj A Dadhania
2016-12-05 11:25 ` [Qemu-devel] [PATCH 12/13] target-ppc: implement xscpsgnqp instruction Nikunj A Dadhania
2016-12-05 18:18 ` Richard Henderson
2016-12-05 11:25 ` [Qemu-devel] [PATCH 13/13] target-ppc: Add xxperm and xxpermr instructions Nikunj A Dadhania
2016-12-06 4:11 ` David Gibson [this message]
2016-12-06 8:55 ` Bharata B Rao
2016-12-06 4:12 ` [Qemu-devel] [PATCH ppc-for-2.9 00/13] POWER9 TCG enablements - part9 David Gibson
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