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From: Peter Xu <peterx@redhat.com>
To: Jason Wang <jasowang@redhat.com>
Cc: qemu-devel@nongnu.org, famz@redhat.com, mst@redhat.com
Subject: Re: [Qemu-devel] [PATCH for-2.9 1/2] intel_iommu: check validity for GAW bits in CE
Date: Mon, 12 Dec 2016 09:47:58 +0800	[thread overview]
Message-ID: <20161212014758.GI28693@pxdev.xzpeter.org> (raw)
In-Reply-To: <2ecc2092-ef56-7289-0a6f-8ceaa5d0218e@redhat.com>

On Thu, Dec 08, 2016 at 10:21:35AM +0800, Jason Wang wrote:
> 
> 
> On 2016年12月08日 10:16, Peter Xu wrote:
> >On Thu, Dec 08, 2016 at 10:02:15AM +0800, Jason Wang wrote:
> >>
> >>On 2016年12月07日 13:52, Peter Xu wrote:
> >>>Currently vt-d Context Entry (CE) only allows 39/48 bits address width.
> >>>If guest software configured more than that, we complain and force
> >>>shrink to the maximum supported, which is 48bits.
> >>>
> >>>Signed-off-by: Peter Xu <peterx@redhat.com>
> >>>---
> >>>  hw/i386/intel_iommu.c          | 12 +++++++++++-
> >>>  hw/i386/intel_iommu_internal.h |  2 ++
> >>>  2 files changed, 13 insertions(+), 1 deletion(-)
> >>>
> >>>diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> >>>index 5f3e351..98d45ef 100644
> >>>--- a/hw/i386/intel_iommu.c
> >>>+++ b/hw/i386/intel_iommu.c
> >>>@@ -601,7 +601,17 @@ static inline uint32_t vtd_get_level_from_context_entry(VTDContextEntry *ce)
> >>>  static inline uint32_t vtd_get_agaw_from_context_entry(VTDContextEntry *ce)
> >>>  {
> >>>-    return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9;
> >>>+    uint8_t aw = (ce->hi & VTD_CONTEXT_ENTRY_AW);
> >>>+    /*
> >>>+     * According to vt-d spec 10.4.2 bits 12:8, SAGAW only allows
> >>>+     * 39/48 bits.
> >>>+     */
> >>>+    if (aw > VTD_CE_AW_48BIT) {
> >>>+        error_report("Context entry address width not supported (aw=%d), "
> >>>+                     "Shrinking to maximum.", aw);
> >>>+        aw = VTD_CE_AW_48BIT;
> >>>+    }
> >>Is this behavior specified by spec?
> >That's how I understand spec 10.4.2 bits 12:8 (as mentioned in above
> >comment). Only 39/48 bits AGAW are allowed, and others are reserved.
> >
> >When writting up this patch, I thought illegal value for this aw bits
> >(from guest software) might cause trouble, but I was wrong, since we
> >have a "MIN(ce_agaw, VTD_MGAW)" check later on. So that won't be a
> >problem, and this patch is not that necessary now.
> >
> >Thanks,
> >
> >-- peterx
> 
> Yes, and it can even report DMAR fault to guest which is better.

Yes. Will respin, thanks. :-)

-- peterx

  reply	other threads:[~2016-12-12  1:48 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-12-07  5:52 [Qemu-devel] [PATCH for-2.9 0/2] VT-d extend GAW to 48 bits Peter Xu
2016-12-07  5:52 ` [Qemu-devel] [PATCH for-2.9 1/2] intel_iommu: check validity for GAW bits in CE Peter Xu
2016-12-08  2:02   ` Jason Wang
2016-12-08  2:16     ` Peter Xu
2016-12-08  2:21       ` Jason Wang
2016-12-12  1:47         ` Peter Xu [this message]
2016-12-07  5:52 ` [Qemu-devel] [PATCH for-2.9 2/2] intel_iommu: extend supported guest aw to 48 bits Peter Xu
2016-12-08  2:00   ` Jason Wang
2016-12-11  3:13   ` Michael S. Tsirkin
2016-12-12  2:01     ` Peter Xu
2016-12-12 19:35       ` Alex Williamson
2016-12-13  3:33         ` Peter Xu
2016-12-13  3:51           ` Alex Williamson
2016-12-13  5:24             ` Peter Xu
2016-12-13  5:48               ` Alex Williamson
2016-12-13  6:12                 ` Peter Xu
2016-12-13 13:17                   ` Alex Williamson
2016-12-13 14:38                     ` Michael S. Tsirkin
2016-12-13  5:00         ` Tian, Kevin
2016-12-13  5:31           ` Alex Williamson
2016-12-07  8:40 ` [Qemu-devel] [PATCH for-2.9 0/2] VT-d extend GAW " Fam Zheng

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