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[81.231.233.234]) by smtp.gmail.com with ESMTPSA id t126sm9929568lff.26.2016.12.13.04.37.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 13 Dec 2016 04:37:27 -0800 (PST) Date: Tue, 13 Dec 2016 13:37:26 +0100 From: "Edgar E. Iglesias" To: Peter Maydell Message-ID: <20161213123726.GM9606@toto> References: <1481625384-15077-1-git-send-email-peter.maydell@linaro.org> <1481625384-15077-11-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1481625384-15077-11-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.194 Subject: Re: [Qemu-arm] [PATCH 10/23] target-arm: Expose output GPIO line for VCPU maintenance interrupt X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Christoffer Dall , patches@linaro.org Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: fwixlnYhOmKU On Tue, Dec 13, 2016 at 10:36:11AM +0000, Peter Maydell wrote: > The GICv3 support for virtualization includes an outbound > maintenance interrupt signal which is asserted when the > CPU interface wants to signal to the hypervisor that it > needs attention. Expose this as an outbound GPIO line from > the CPU object which can be wired up as a physical interrupt > line by the board code (as we do already for the CPU timers). > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target-arm/cpu.h | 2 ++ > target-arm/cpu.c | 3 +++ > 2 files changed, 5 insertions(+) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index ca5c849..c38488a 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -555,6 +555,8 @@ struct ARMCPU { > QEMUTimer *gt_timer[NUM_GTIMERS]; > /* GPIO outputs for generic timer */ > qemu_irq gt_timer_outputs[NUM_GTIMERS]; > + /* GPIO output for GICv3 maintenance interrupt signal */ > + qemu_irq gicv3_maintenance_interrupt; > > /* MemoryRegion to use for secure physical accesses */ > MemoryRegion *secure_memory; > diff --git a/target-arm/cpu.c b/target-arm/cpu.c > index 99f0dbe..5e0d21d 100644 > --- a/target-arm/cpu.c > +++ b/target-arm/cpu.c > @@ -466,6 +466,9 @@ static void arm_cpu_initfn(Object *obj) > arm_gt_stimer_cb, cpu); > qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, > ARRAY_SIZE(cpu->gt_timer_outputs)); > + > + qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, > + "gicv3-maintenance-interrupt", 1); > #endif > > /* DTB consumers generally don't in fact care what the 'compatible' > -- > 2.7.4 > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56325) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cGmLv-0006bR-WB for qemu-devel@nongnu.org; Tue, 13 Dec 2016 07:38:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cGmLv-0005vS-2h for qemu-devel@nongnu.org; Tue, 13 Dec 2016 07:38:39 -0500 Date: Tue, 13 Dec 2016 13:37:26 +0100 From: "Edgar E. Iglesias" Message-ID: <20161213123726.GM9606@toto> References: <1481625384-15077-1-git-send-email-peter.maydell@linaro.org> <1481625384-15077-11-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1481625384-15077-11-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH 10/23] target-arm: Expose output GPIO line for VCPU maintenance interrupt List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org, Christoffer Dall , Andrew Jones On Tue, Dec 13, 2016 at 10:36:11AM +0000, Peter Maydell wrote: > The GICv3 support for virtualization includes an outbound > maintenance interrupt signal which is asserted when the > CPU interface wants to signal to the hypervisor that it > needs attention. Expose this as an outbound GPIO line from > the CPU object which can be wired up as a physical interrupt > line by the board code (as we do already for the CPU timers). > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target-arm/cpu.h | 2 ++ > target-arm/cpu.c | 3 +++ > 2 files changed, 5 insertions(+) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index ca5c849..c38488a 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -555,6 +555,8 @@ struct ARMCPU { > QEMUTimer *gt_timer[NUM_GTIMERS]; > /* GPIO outputs for generic timer */ > qemu_irq gt_timer_outputs[NUM_GTIMERS]; > + /* GPIO output for GICv3 maintenance interrupt signal */ > + qemu_irq gicv3_maintenance_interrupt; > > /* MemoryRegion to use for secure physical accesses */ > MemoryRegion *secure_memory; > diff --git a/target-arm/cpu.c b/target-arm/cpu.c > index 99f0dbe..5e0d21d 100644 > --- a/target-arm/cpu.c > +++ b/target-arm/cpu.c > @@ -466,6 +466,9 @@ static void arm_cpu_initfn(Object *obj) > arm_gt_stimer_cb, cpu); > qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, > ARRAY_SIZE(cpu->gt_timer_outputs)); > + > + qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, > + "gicv3-maintenance-interrupt", 1); > #endif > > /* DTB consumers generally don't in fact care what the 'compatible' > -- > 2.7.4 >