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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 01/14] drm/i915: Track visible planes in a bitmask
Date: Thu, 15 Dec 2016 17:02:45 +0200	[thread overview]
Message-ID: <20161215150245.GG31595@intel.com> (raw)
In-Reply-To: <fe78d8f6-5139-5e19-79a3-1659d739059b@linux.intel.com>

On Thu, Dec 15, 2016 at 03:56:03PM +0100, Maarten Lankhorst wrote:
> Op 12-12-16 om 21:35 schreef ville.syrjala@linux.intel.com:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > In a lot of place we wish to know which planes on the crtc are actually
> > visible, or how many of them there are. Let's start tracking that in a
> > bitmask in the crtc state.
> >
> > We already track enabled planes (ie. ones with an fb and crtc specified by
> > the user) but that's not quite the same thing as enabled planes may
> > still end up being invisible due to clipping and whatnot.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_atomic_plane.c |  6 +++
> >  drivers/gpu/drm/i915/intel_display.c      | 79 +++++++++++++++++++++----------
> >  drivers/gpu/drm/i915/intel_drv.h          |  3 ++
> >  3 files changed, 64 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
> > index dbe9fb41ae53..7ec12edda4d4 100644
> > --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> > @@ -181,6 +181,12 @@ static int intel_plane_atomic_check(struct drm_plane *plane,
> >  	if (ret)
> >  		return ret;
> >  
> > +	/* FIXME pre-g4x don't work like this */
> > +	if (intel_state->base.visible)
> > +		crtc_state->active_planes |= BIT(intel_plane->id);
> > +	else
> > +		crtc_state->active_planes &= ~BIT(intel_plane->id);
> > +
> >  	return intel_plane_atomic_calc_changes(&crtc_state->base, state);
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index bc1af87789bc..3f027341b0f3 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2741,6 +2741,29 @@ update_state_fb(struct drm_plane *plane)
> >  }
> >  
> >  static void
> > +intel_set_plane_visible(struct intel_crtc_state *crtc_state,
> > +			struct intel_plane_state *plane_state,
> > +			bool visible)
> > +{
> > +	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> > +
> > +	plane_state->base.visible = visible;
> > +
> > +	/* FIXME pre-g4x don't work like this */
> > +	if (visible) {
> > +		crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
> > +		crtc_state->active_planes |= BIT(plane->id);
> > +	} else {
> > +		crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
> > +		crtc_state->active_planes &= ~BIT(plane->id);
> > +	}
> > +
> > +	DRM_DEBUG_KMS("%s active planes 0x%x\n",
> > +		      crtc_state->base.crtc->name,
> > +		      crtc_state->active_planes);
> > +}
> > +
> > +static void
> >  intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> >  			     struct intel_initial_plane_config *plane_config)
> >  {
> > @@ -2798,8 +2821,9 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> >  	 * simplest solution is to just disable the primary plane now and
> >  	 * pretend the BIOS never had it enabled.
> >  	 */
> > -	to_intel_plane_state(plane_state)->base.visible = false;
> > -	crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
> > +	intel_set_plane_visible(to_intel_crtc_state(crtc_state),
> > +				to_intel_plane_state(plane_state),
> > +				false);
> >  	intel_pre_disable_primary_noatomic(&intel_crtc->base);
> >  	intel_plane->disable_plane(primary, &intel_crtc->base);
> >  
> > @@ -2826,7 +2850,11 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> >  	drm_framebuffer_reference(fb);
> >  	primary->fb = primary->state->fb = fb;
> >  	primary->crtc = primary->state->crtc = &intel_crtc->base;
> > -	intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
> > +
> > +	intel_set_plane_visible(to_intel_crtc_state(intel_crtc->base.state),
> > +				to_intel_plane_state(primary->state),
> > +				true);
> > +
> >  	atomic_or(to_intel_plane(primary)->frontbuffer_bit,
> >  		  &obj->frontbuffer_bits);
> >  }
> > @@ -12440,11 +12468,11 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
> >  	struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
> >  	struct drm_crtc *crtc = crtc_state->crtc;
> >  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > -	struct drm_plane *plane = plane_state->plane;
> > +	struct intel_plane *plane = to_intel_plane(plane_state->plane);
> >  	struct drm_device *dev = crtc->dev;
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> >  	struct intel_plane_state *old_plane_state =
> > -		to_intel_plane_state(plane->state);
> > +		to_intel_plane_state(plane->base.state);
> >  	bool mode_changed = needs_modeset(crtc_state);
> >  	bool was_crtc_enabled = crtc->state->active;
> >  	bool is_crtc_enabled = crtc_state->active;
> > @@ -12452,7 +12480,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
> >  	struct drm_framebuffer *fb = plane_state->fb;
> >  	int ret;
> >  
> > -	if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
> > +	if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
> >  		ret = skl_update_scaler_plane(
> >  			to_intel_crtc_state(crtc_state),
> >  			to_intel_plane_state(plane_state));
> > @@ -12476,8 +12504,10 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
> >  	 * per-plane wm computation to the .check_plane() hook, and
> >  	 * only combine the results from all planes in the current place?
> >  	 */
> > -	if (!is_crtc_enabled)
> > +	if (!is_crtc_enabled) {
> >  		to_intel_plane_state(plane_state)->base.visible = visible = false;
> > +		to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
> > +	}
> >  
> >  	if (!was_visible && !visible)
> >  		return 0;
> > @@ -12489,13 +12519,12 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
> >  	turn_on = visible && (!was_visible || mode_changed);
> >  
> >  	DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
> > -			 intel_crtc->base.base.id,
> > -			 intel_crtc->base.name,
> > -			 plane->base.id, plane->name,
> > +			 intel_crtc->base.base.id, intel_crtc->base.name,
> > +			 plane->base.base.id, plane->base.name,
> >  			 fb ? fb->base.id : -1);
> >  
> >  	DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
> > -			 plane->base.id, plane->name,
> > +			 plane->base.base.id, plane->base.name,
> >  			 was_visible, visible,
> >  			 turn_off, turn_on, mode_changed);
> >  
> > @@ -12503,15 +12532,15 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
> >  		pipe_config->update_wm_pre = true;
> >  
> >  		/* must disable cxsr around plane enable/disable */
> > -		if (plane->type != DRM_PLANE_TYPE_CURSOR)
> > +		if (plane->id != PLANE_CURSOR)
> >  			pipe_config->disable_cxsr = true;
> >  	} else if (turn_off) {
> >  		pipe_config->update_wm_post = true;
> >  
> >  		/* must disable cxsr around plane enable/disable */
> > -		if (plane->type != DRM_PLANE_TYPE_CURSOR)
> > +		if (plane->id != PLANE_CURSOR)
> >  			pipe_config->disable_cxsr = true;
> > -	} else if (intel_wm_need_update(plane, plane_state)) {
> > +	} else if (intel_wm_need_update(&plane->base, plane_state)) {
> >  		/* FIXME bollocks */
> >  		pipe_config->update_wm_pre = true;
> >  		pipe_config->update_wm_post = true;
> > @@ -12523,7 +12552,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
> >  		to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
> >  
> >  	if (visible || was_visible)
> > -		pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
> > +		pipe_config->fb_bits |= plane->frontbuffer_bit;
> >  
> >  	/*
> >  	 * WaCxSRDisabledForSpriteScaling:ivb
> > @@ -12531,7 +12560,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
> >  	 * cstate->update_wm was already set above, so this flag will
> >  	 * take effect when we commit and program watermarks.
> >  	 */
> > -	if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
> > +	if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
> >  	    needs_scaling(to_intel_plane_state(plane_state)) &&
> >  	    !needs_scaling(old_plane_state))
> >  		pipe_config->disable_lp_wm = true;
> > @@ -16876,15 +16905,14 @@ static bool primary_get_hw_state(struct intel_plane *plane)
> >  /* FIXME read out full plane state for all planes */
> >  static void readout_plane_state(struct intel_crtc *crtc)
> >  {
> > -	struct drm_plane *primary = crtc->base.primary;
> > -	struct intel_plane_state *plane_state =
> > -		to_intel_plane_state(primary->state);
> > +	struct intel_plane *primary = to_intel_plane(crtc->base.primary);
> > +	bool visible;
> >  
> > -	plane_state->base.visible = crtc->active &&
> > -		primary_get_hw_state(to_intel_plane(primary));
> > +	visible = crtc->active && primary_get_hw_state(primary);
> >  
> > -	if (plane_state->base.visible)
> > -		crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
> > +	intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
> > +				to_intel_plane_state(primary->base.state),
> > +				visible);
> >  }
> >  
> >  static void intel_modeset_readout_hw_state(struct drm_device *dev)
> > @@ -17171,7 +17199,10 @@ void intel_modeset_gem_init(struct drm_device *dev)
> >  			c->primary->fb = NULL;
> >  			c->primary->crtc = c->primary->state->crtc = NULL;
> >  			update_state_fb(c->primary);
> > -			c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
> > +
> > +			intel_set_plane_visible(to_intel_crtc_state(c->state),
> > +						to_intel_plane_state(c->primary->state),
> > +						false);
> >  		}
> >  	}
> >  }
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 8f4ddca0f521..20ba8f48bc3b 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -669,6 +669,9 @@ struct intel_crtc_state {
> >  
> >  	/* Gamma mode programmed on the pipe */
> >  	uint32_t gamma_mode;
> > +
> > +	/* bitmask of visible planes (enum plane_id) */
> > +	u8 active_planes;
> Can we change this to uint32_t 1<<drm_plane_index like the other masks?
> 
> plane_mask, connector_mask and encoder_mask use 1 << index.
> Perhaps name it active_planes_mask too.

The way I use it wouldn't lend itself well to that. I don't have any
plane structs around in a bunch of the places where this gets used.

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2016-12-15 15:02 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-12-12 20:35 [PATCH 00/14] drm/i915: VLV/CHV two-stage watermarks ville.syrjala
2016-12-12 20:35 ` [PATCH 01/14] drm/i915: Track visible planes in a bitmask ville.syrjala
2016-12-15 14:56   ` Maarten Lankhorst
2016-12-15 15:02     ` Ville Syrjälä [this message]
2016-12-15 17:11       ` Maarten Lankhorst
2016-12-15 17:20         ` Ville Syrjälä
2016-12-12 20:35 ` [PATCH 02/14] drm/i915: Track plane fifo sizes under intel_crtc ville.syrjala
2016-12-15 14:58   ` Maarten Lankhorst
2017-02-16 17:48     ` Ville Syrjälä
2016-12-12 20:35 ` [PATCH 03/14] drm/i915: Move vlv wms from crtc->wm_state to crtc->wm.active.vlv ville.syrjala
2016-12-12 20:35 ` [PATCH 04/14] drm/i915: Plop vlv wm state into crtc_state ville.syrjala
2016-12-12 20:35 ` [PATCH 05/14] drm/i915: Plop vlv/chv fifo sizes into crtc state ville.syrjala
2016-12-12 20:35 ` [PATCH 06/14] drm/i915: Compute VLV/CHV FIFO sizes based on the PM2 watermarks ville.syrjala
2016-12-12 20:35 ` [PATCH 07/14] drm/i915: Compute vlv/chv wms the atomic way ville.syrjala
2016-12-15 15:30   ` Maarten Lankhorst
2016-12-15 15:38     ` Ville Syrjälä
2016-12-15 15:45       ` Maarten Lankhorst
2016-12-15 16:09         ` Ville Syrjälä
2016-12-15 17:12           ` Maarten Lankhorst
2016-12-15 17:17             ` Ville Syrjälä
2016-12-29 15:42           ` Maarten Lankhorst
2016-12-12 20:35 ` [PATCH 08/14] drm/i915: Skip useless watermark/FIFO related work on VLV/CHV when not needed ville.syrjala
2016-12-15 15:37   ` Maarten Lankhorst
2017-02-16 17:54     ` Ville Syrjälä
2016-12-12 20:35 ` [PATCH 09/14] drm/i915: Compute proper intermediate wms for vlv/cvh ville.syrjala
2016-12-12 20:35 ` [PATCH 10/14] drm/i915: Nuke crtc->wm.cxsr_allowed ville.syrjala
2016-12-12 20:35 ` [PATCH 11/14] drm/i915: Only use update_wm_{pre, post} for pre-ilk platforms ville.syrjala
2016-12-12 20:35 ` [PATCH 12/14] drm/i915: Sanitize VLV/CHV watermarks properly ville.syrjala
2016-12-12 20:35 ` [PATCH 13/14] drm/i915: Workaround VLV/CHV sprite1->sprite0 enable underrun ville.syrjala
2016-12-15 15:34   ` Maarten Lankhorst
2016-12-15 15:47     ` Ville Syrjälä
2016-12-15 16:13       ` Maarten Lankhorst
2016-12-15 16:18         ` Ville Syrjälä
2016-12-12 20:35 ` [PATCH 14/14] drm/i915: Kill level 0 wm hack for VLV/CHV ville.syrjala
2016-12-15 17:10   ` Maarten Lankhorst
2016-12-12 20:35 ` [PATCH i-g-t] tests: Add kms_plane_blinker ville.syrjala
2016-12-15 15:17   ` Maarten Lankhorst
2016-12-15 15:23     ` Ville Syrjälä
2016-12-15 15:28       ` Maarten Lankhorst
2016-12-15 15:36         ` Ville Syrjälä
2016-12-15 15:41           ` Maarten Lankhorst
2016-12-15 16:42             ` Ville Syrjälä
2016-12-15 17:26               ` Ville Syrjälä
2016-12-19  7:07                 ` Maarten Lankhorst
2016-12-12 21:15 ` ✗ Fi.CI.BAT: warning for drm/i915: VLV/CHV two-stage watermarks Patchwork
2016-12-13  7:42   ` Saarinen, Jani
2016-12-13  8:40     ` Chris Wilson

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