From mboxrd@z Thu Jan 1 00:00:00 1970 From: lee.jones@linaro.org (Lee Jones) Date: Tue, 3 Jan 2017 17:49:06 +0000 Subject: [PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC) In-Reply-To: <20161206025321.1792-5-andrew@aj.id.au> References: <20161206025321.1792-1-andrew@aj.id.au> <20161206025321.1792-5-andrew@aj.id.au> Message-ID: <20170103174906.GB27589@dell> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, 06 Dec 2016, Andrew Jeffery wrote: > The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends > on bits in both the System Control Unit and the LPC Host Controller. > > The Aspeed LPC Host Controller is described as a child node of the > LPC host-range syscon device for arbitration of access by the host > controller and pinmux drivers. > > Signed-off-by: Andrew Jeffery Applied with Acks, thanks. > --- > .../devicetree/bindings/mfd/aspeed-lpc.txt | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > index a97131aba446..9de318ef72da 100644 > --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > @@ -109,3 +109,25 @@ lpc: lpc at 1e789000 { > }; > }; > > +Host Node Children > +================== > + > +LPC Host Controller > +------------------- > + > +The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour > +between the host and the baseboard management controller. The registers exist > +in the "host" portion of the Aspeed LPC controller, which must be the parent of > +the LPC host controller node. > + > +Required properties: > +- compatible: "aspeed,ast2500-lhc"; > +- reg: contains offset/length value of the LHC memory > + region. > + > +Example: > + > +lhc: lhc at 20 { > + compatible = "aspeed,ast2500-lhc"; > + reg = <0x20 0x24 0x48 0x8>; > +}; -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org ? Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lee Jones Subject: Re: [PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC) Date: Tue, 3 Jan 2017 17:49:06 +0000 Message-ID: <20170103174906.GB27589@dell> References: <20161206025321.1792-1-andrew@aj.id.au> <20161206025321.1792-5-andrew@aj.id.au> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <20161206025321.1792-5-andrew@aj.id.au> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Andrew Jeffery Cc: Mark Rutland , devicetree@vger.kernel.org, Corey Minyard , Linus Walleij , linux-kernel@vger.kernel.org, Rob Herring , =?iso-8859-1?Q?C=E9dric?= Le Goater , linux-arm-kernel@lists.infradead.org, Joel Stanley List-Id: devicetree@vger.kernel.org T24gVHVlLCAwNiBEZWMgMjAxNiwgQW5kcmV3IEplZmZlcnkgd3JvdGU6Cgo+IFRoZSBMUEMgYnVz IHBpbm11eCBjb25maWd1cmF0aW9uIG9uIGZpZnRoIGdlbmVyYXRpb24gQXNwZWVkIFNvQ3MgZGVw ZW5kcwo+IG9uIGJpdHMgaW4gYm90aCB0aGUgU3lzdGVtIENvbnRyb2wgVW5pdCBhbmQgdGhlIExQ QyBIb3N0IENvbnRyb2xsZXIuCj4gCj4gVGhlIEFzcGVlZCBMUEMgSG9zdCBDb250cm9sbGVyIGlz IGRlc2NyaWJlZCBhcyBhIGNoaWxkIG5vZGUgb2YgdGhlCj4gTFBDIGhvc3QtcmFuZ2Ugc3lzY29u IGRldmljZSBmb3IgYXJiaXRyYXRpb24gb2YgYWNjZXNzIGJ5IHRoZSBob3N0Cj4gY29udHJvbGxl ciBhbmQgcGlubXV4IGRyaXZlcnMuCj4gCj4gU2lnbmVkLW9mZi1ieTogQW5kcmV3IEplZmZlcnkg PGFuZHJld0Bhai5pZC5hdT4KCkFwcGxpZWQgd2l0aCBBY2tzLCB0aGFua3MuCgo+IC0tLQo+ICAu Li4vZGV2aWNldHJlZS9iaW5kaW5ncy9tZmQvYXNwZWVkLWxwYy50eHQgICAgICAgICB8IDIyICsr KysrKysrKysrKysrKysrKysrKysKPiAgMSBmaWxlIGNoYW5nZWQsIDIyIGluc2VydGlvbnMoKykK PiAKPiBkaWZmIC0tZ2l0IGEvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL21mZC9h c3BlZWQtbHBjLnR4dCBiL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9tZmQvYXNw ZWVkLWxwYy50eHQKPiBpbmRleCBhOTcxMzFhYmE0NDYuLjlkZTMxOGVmNzJkYSAxMDA2NDQKPiAt LS0gYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvbWZkL2FzcGVlZC1scGMudHh0 Cj4gKysrIGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL21mZC9hc3BlZWQtbHBj LnR4dAo+IEBAIC0xMDksMyArMTA5LDI1IEBAIGxwYzogbHBjQDFlNzg5MDAwIHsKPiAgCX07Cj4g IH07Cj4gIAo+ICtIb3N0IE5vZGUgQ2hpbGRyZW4KPiArPT09PT09PT09PT09PT09PT09Cj4gKwo+ ICtMUEMgSG9zdCBDb250cm9sbGVyCj4gKy0tLS0tLS0tLS0tLS0tLS0tLS0KPiArCj4gK1RoZSBB c3BlZWQgTFBDIEhvc3QgQ29udHJvbGxlciBjb25maWd1cmVzIHRoZSBMb3cgUGluIENvdW50IChM UEMpIGJ1cyBiZWhhdmlvdXIKPiArYmV0d2VlbiB0aGUgaG9zdCBhbmQgdGhlIGJhc2Vib2FyZCBt YW5hZ2VtZW50IGNvbnRyb2xsZXIuIFRoZSByZWdpc3RlcnMgZXhpc3QKPiAraW4gdGhlICJob3N0 IiBwb3J0aW9uIG9mIHRoZSBBc3BlZWQgTFBDIGNvbnRyb2xsZXIsIHdoaWNoIG11c3QgYmUgdGhl IHBhcmVudCBvZgo+ICt0aGUgTFBDIGhvc3QgY29udHJvbGxlciBub2RlLgo+ICsKPiArUmVxdWly ZWQgcHJvcGVydGllczoKPiArLSBjb21wYXRpYmxlOgkJImFzcGVlZCxhc3QyNTAwLWxoYyI7Cj4g Ky0gcmVnOgkJCWNvbnRhaW5zIG9mZnNldC9sZW5ndGggdmFsdWUgb2YgdGhlIExIQyBtZW1vcnkK PiArCQkJcmVnaW9uLgo+ICsKPiArRXhhbXBsZToKPiArCj4gK2xoYzogbGhjQDIwIHsKPiArCWNv bXBhdGlibGUgPSAiYXNwZWVkLGFzdDI1MDAtbGhjIjsKPiArCXJlZyA9IDwweDIwIDB4MjQgMHg0 OCAweDg+Owo+ICt9OwoKLS0gCkxlZSBKb25lcwpMaW5hcm8gU1RNaWNyb2VsZWN0cm9uaWNzIExh bmRpbmcgVGVhbSBMZWFkCkxpbmFyby5vcmcg4pSCIE9wZW4gc291cmNlIHNvZnR3YXJlIGZvciBB Uk0gU29DcwpGb2xsb3cgTGluYXJvOiBGYWNlYm9vayB8IFR3aXR0ZXIgfCBCbG9nCgpfX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2VybmVs IG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDov L2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965421AbdACRq2 (ORCPT ); Tue, 3 Jan 2017 12:46:28 -0500 Received: from mail-wm0-f51.google.com ([74.125.82.51]:37707 "EHLO mail-wm0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753400AbdACRpZ (ORCPT ); Tue, 3 Jan 2017 12:45:25 -0500 Date: Tue, 3 Jan 2017 17:49:06 +0000 From: Lee Jones To: Andrew Jeffery Cc: Rob Herring , Mark Rutland , Linus Walleij , Corey Minyard , =?iso-8859-1?Q?C=E9dric?= Le Goater , Joel Stanley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC) Message-ID: <20170103174906.GB27589@dell> References: <20161206025321.1792-1-andrew@aj.id.au> <20161206025321.1792-5-andrew@aj.id.au> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20161206025321.1792-5-andrew@aj.id.au> User-Agent: Mutt/1.6.2 (2016-07-01) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 06 Dec 2016, Andrew Jeffery wrote: > The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends > on bits in both the System Control Unit and the LPC Host Controller. > > The Aspeed LPC Host Controller is described as a child node of the > LPC host-range syscon device for arbitration of access by the host > controller and pinmux drivers. > > Signed-off-by: Andrew Jeffery Applied with Acks, thanks. > --- > .../devicetree/bindings/mfd/aspeed-lpc.txt | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > index a97131aba446..9de318ef72da 100644 > --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > @@ -109,3 +109,25 @@ lpc: lpc@1e789000 { > }; > }; > > +Host Node Children > +================== > + > +LPC Host Controller > +------------------- > + > +The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour > +between the host and the baseboard management controller. The registers exist > +in the "host" portion of the Aspeed LPC controller, which must be the parent of > +the LPC host controller node. > + > +Required properties: > +- compatible: "aspeed,ast2500-lhc"; > +- reg: contains offset/length value of the LHC memory > + region. > + > +Example: > + > +lhc: lhc@20 { > + compatible = "aspeed,ast2500-lhc"; > + reg = <0x20 0x24 0x48 0x8>; > +}; -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog