From mboxrd@z Thu Jan 1 00:00:00 1970 From: lee.jones@linaro.org (Lee Jones) Date: Tue, 3 Jan 2017 17:49:54 +0000 Subject: [PATCH v3 5/6] mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX) In-Reply-To: <20161206025321.1792-6-andrew@aj.id.au> References: <20161206025321.1792-1-andrew@aj.id.au> <20161206025321.1792-6-andrew@aj.id.au> Message-ID: <20170103174954.GF27589@dell> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, 06 Dec 2016, Andrew Jeffery wrote: > The Aspeed SoC Display Controller is presented as a syscon device to > arbitrate access by display and pinmux drivers. Video pinmux > configuration on fifth generation SoCs depends on bits in both the > System Control Unit and the Display Controller. > > Signed-off-by: Andrew Jeffery > Acked-by: Rob Herring Applied with Acks, thanks. > --- > .../devicetree/bindings/mfd/syscon/aspeed-gfx.txt | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mfd/syscon/aspeed-gfx.txt > > diff --git a/Documentation/devicetree/bindings/mfd/syscon/aspeed-gfx.txt b/Documentation/devicetree/bindings/mfd/syscon/aspeed-gfx.txt > new file mode 100644 > index 000000000000..aea5370efd97 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mfd/syscon/aspeed-gfx.txt > @@ -0,0 +1,17 @@ > +* Device tree bindings for Aspeed SoC Display Controller (GFX) > + > +The Aspeed SoC Display Controller primarily does as its name suggests, but also > +participates in pinmux requests on the g5 SoCs. It is therefore considered a > +syscon device. > + > +Required properties: > +- compatible: "aspeed,ast2500-gfx", "syscon" > +- reg: contains offset/length value of the GFX memory > + region. > + > +Example: > + > +gfx: display at 1e6e6000 { > + compatible = "aspeed,ast2500-gfx", "syscon"; > + reg = <0x1e6e6000 0x1000>; > +}; -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org ? Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lee Jones Subject: Re: [PATCH v3 5/6] mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX) Date: Tue, 3 Jan 2017 17:49:54 +0000 Message-ID: <20170103174954.GF27589@dell> References: <20161206025321.1792-1-andrew@aj.id.au> <20161206025321.1792-6-andrew@aj.id.au> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <20161206025321.1792-6-andrew@aj.id.au> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Andrew Jeffery Cc: Mark Rutland , devicetree@vger.kernel.org, Corey Minyard , Linus Walleij , linux-kernel@vger.kernel.org, Rob Herring , =?iso-8859-1?Q?C=E9dric?= Le Goater , linux-arm-kernel@lists.infradead.org, Joel Stanley List-Id: devicetree@vger.kernel.org T24gVHVlLCAwNiBEZWMgMjAxNiwgQW5kcmV3IEplZmZlcnkgd3JvdGU6Cgo+IFRoZSBBc3BlZWQg U29DIERpc3BsYXkgQ29udHJvbGxlciBpcyBwcmVzZW50ZWQgYXMgYSBzeXNjb24gZGV2aWNlIHRv Cj4gYXJiaXRyYXRlIGFjY2VzcyBieSBkaXNwbGF5IGFuZCBwaW5tdXggZHJpdmVycy4gVmlkZW8g cGlubXV4Cj4gY29uZmlndXJhdGlvbiBvbiBmaWZ0aCBnZW5lcmF0aW9uIFNvQ3MgZGVwZW5kcyBv biBiaXRzIGluIGJvdGggdGhlCj4gU3lzdGVtIENvbnRyb2wgVW5pdCBhbmQgdGhlIERpc3BsYXkg Q29udHJvbGxlci4KPiAKPiBTaWduZWQtb2ZmLWJ5OiBBbmRyZXcgSmVmZmVyeSA8YW5kcmV3QGFq LmlkLmF1Pgo+IEFja2VkLWJ5OiBSb2IgSGVycmluZyA8cm9iaEBrZXJuZWwub3JnPgoKQXBwbGll ZCB3aXRoIEFja3MsIHRoYW5rcy4KCj4gLS0tCj4gIC4uLi9kZXZpY2V0cmVlL2JpbmRpbmdzL21m ZC9zeXNjb24vYXNwZWVkLWdmeC50eHQgICAgICAgfCAxNyArKysrKysrKysrKysrKysrKwo+ICAx IGZpbGUgY2hhbmdlZCwgMTcgaW5zZXJ0aW9ucygrKQo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgRG9j dW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL21mZC9zeXNjb24vYXNwZWVkLWdmeC50eHQK PiAKPiBkaWZmIC0tZ2l0IGEvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL21mZC9z eXNjb24vYXNwZWVkLWdmeC50eHQgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3Mv bWZkL3N5c2Nvbi9hc3BlZWQtZ2Z4LnR4dAo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4gaW5kZXgg MDAwMDAwMDAwMDAwLi5hZWE1MzcwZWZkOTcKPiAtLS0gL2Rldi9udWxsCj4gKysrIGIvRG9jdW1l bnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL21mZC9zeXNjb24vYXNwZWVkLWdmeC50eHQKPiBA QCAtMCwwICsxLDE3IEBACj4gKyogRGV2aWNlIHRyZWUgYmluZGluZ3MgZm9yIEFzcGVlZCBTb0Mg RGlzcGxheSBDb250cm9sbGVyIChHRlgpCj4gKwo+ICtUaGUgQXNwZWVkIFNvQyBEaXNwbGF5IENv bnRyb2xsZXIgcHJpbWFyaWx5IGRvZXMgYXMgaXRzIG5hbWUgc3VnZ2VzdHMsIGJ1dCBhbHNvCj4g K3BhcnRpY2lwYXRlcyBpbiBwaW5tdXggcmVxdWVzdHMgb24gdGhlIGc1IFNvQ3MuIEl0IGlzIHRo ZXJlZm9yZSBjb25zaWRlcmVkIGEKPiArc3lzY29uIGRldmljZS4KPiArCj4gK1JlcXVpcmVkIHBy b3BlcnRpZXM6Cj4gKy0gY29tcGF0aWJsZToJCSJhc3BlZWQsYXN0MjUwMC1nZngiLCAic3lzY29u Igo+ICstIHJlZzoJCQljb250YWlucyBvZmZzZXQvbGVuZ3RoIHZhbHVlIG9mIHRoZSBHRlggbWVt b3J5Cj4gKwkJCXJlZ2lvbi4KPiArCj4gK0V4YW1wbGU6Cj4gKwo+ICtnZng6IGRpc3BsYXlAMWU2 ZTYwMDAgewo+ICsJY29tcGF0aWJsZSA9ICJhc3BlZWQsYXN0MjUwMC1nZngiLCAic3lzY29uIjsK PiArCXJlZyA9IDwweDFlNmU2MDAwIDB4MTAwMD47Cj4gK307CgotLSAKTGVlIEpvbmVzCkxpbmFy byBTVE1pY3JvZWxlY3Ryb25pY3MgTGFuZGluZyBUZWFtIExlYWQKTGluYXJvLm9yZyDilIIgT3Bl biBzb3VyY2Ugc29mdHdhcmUgZm9yIEFSTSBTb0NzCkZvbGxvdyBMaW5hcm86IEZhY2Vib29rIHwg VHdpdHRlciB8IEJsb2cKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fCmxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlz dHMuaW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3Rp bmZvL2xpbnV4LWFybS1rZXJuZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760049AbdACRrf (ORCPT ); Tue, 3 Jan 2017 12:47:35 -0500 Received: from mail-wm0-f51.google.com ([74.125.82.51]:36651 "EHLO mail-wm0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759800AbdACRqO (ORCPT ); Tue, 3 Jan 2017 12:46:14 -0500 Date: Tue, 3 Jan 2017 17:49:54 +0000 From: Lee Jones To: Andrew Jeffery Cc: Rob Herring , Mark Rutland , Linus Walleij , Corey Minyard , =?iso-8859-1?Q?C=E9dric?= Le Goater , Joel Stanley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 5/6] mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX) Message-ID: <20170103174954.GF27589@dell> References: <20161206025321.1792-1-andrew@aj.id.au> <20161206025321.1792-6-andrew@aj.id.au> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20161206025321.1792-6-andrew@aj.id.au> User-Agent: Mutt/1.6.2 (2016-07-01) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 06 Dec 2016, Andrew Jeffery wrote: > The Aspeed SoC Display Controller is presented as a syscon device to > arbitrate access by display and pinmux drivers. Video pinmux > configuration on fifth generation SoCs depends on bits in both the > System Control Unit and the Display Controller. > > Signed-off-by: Andrew Jeffery > Acked-by: Rob Herring Applied with Acks, thanks. > --- > .../devicetree/bindings/mfd/syscon/aspeed-gfx.txt | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mfd/syscon/aspeed-gfx.txt > > diff --git a/Documentation/devicetree/bindings/mfd/syscon/aspeed-gfx.txt b/Documentation/devicetree/bindings/mfd/syscon/aspeed-gfx.txt > new file mode 100644 > index 000000000000..aea5370efd97 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mfd/syscon/aspeed-gfx.txt > @@ -0,0 +1,17 @@ > +* Device tree bindings for Aspeed SoC Display Controller (GFX) > + > +The Aspeed SoC Display Controller primarily does as its name suggests, but also > +participates in pinmux requests on the g5 SoCs. It is therefore considered a > +syscon device. > + > +Required properties: > +- compatible: "aspeed,ast2500-gfx", "syscon" > +- reg: contains offset/length value of the GFX memory > + region. > + > +Example: > + > +gfx: display@1e6e6000 { > + compatible = "aspeed,ast2500-gfx", "syscon"; > + reg = <0x1e6e6000 0x1000>; > +}; -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog