From: "谢致邦 (XIE Zhibang)" <Yeking@Red54.com>
To: linux-mips@linux-mips.org
Subject: [PATCH] MIPS: Loongson: Merge load addresses
Date: Wed, 4 Jan 2017 21:30:58 +0800 [thread overview]
Message-ID: <20170104133058.GA20822@red54.local> (raw)
Loongson 1 is a 32-bit MIPS CPU family with PRID 0x4220.
Signed-off-by: 谢致邦 (XIE Zhibang) <Yeking@Red54.com>
---
arch/mips/loongson32/Platform | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/mips/loongson32/Platform b/arch/mips/loongson32/Platform
index ffe01c6d..29795d56 100644
--- a/arch/mips/loongson32/Platform
+++ b/arch/mips/loongson32/Platform
@@ -4,5 +4,4 @@ cflags-$(CONFIG_CPU_LOONGSON1) += \
platform-$(CONFIG_MACH_LOONGSON32) += loongson32/
cflags-$(CONFIG_MACH_LOONGSON32) += -I$(srctree)/arch/mips/include/asm/mach-loongson32
-load-$(CONFIG_LOONGSON1_LS1B) += 0xffffffff80100000
-load-$(CONFIG_LOONGSON1_LS1C) += 0xffffffff80100000
+load-$(CONFIG_CPU_LOONGSON1) += 0xffffffff80100000
--
2.11.0
reply other threads:[~2017-01-04 13:31 UTC|newest]
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