From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 1/2] drm_fourcc: Add new P010 video format Date: Wed, 4 Jan 2017 18:46:49 +0200 Message-ID: <20170104164649.GL31595@intel.com> References: <1483347004-32593-1-git-send-email-ayaka@soulik.info> <1483347004-32593-2-git-send-email-ayaka@soulik.info> <20170104155632.GI31595@intel.com> <1f0969b0-31b3-f9ee-653e-3689fe27932d@soulik.info> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 85A646E292 for ; Wed, 4 Jan 2017 16:46:53 +0000 (UTC) Content-Disposition: inline In-Reply-To: <1f0969b0-31b3-f9ee-653e-3689fe27932d@soulik.info> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: ayaka Cc: randy.li@rock-chips.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, daniel.vetter@intel.com, mchehab@kernel.org, linux-media@vger.kernel.org List-Id: dri-devel@lists.freedesktop.org T24gVGh1LCBKYW4gMDUsIDIwMTcgYXQgMTI6MzE6MjdBTSArMDgwMCwgYXlha2Egd3JvdGU6Cj4K Pgo+IE9uIDAxLzA0LzIwMTcgMTE6NTYgUE0sIFZpbGxlIFN5cmrDpGzDpCB3cm90ZToKPiA+IE9u IE1vbiwgSmFuIDAyLCAyMDE3IGF0IDA0OjUwOjAzUE0gKzA4MDAsIFJhbmR5IExpIHdyb3RlOgo+ ID4+IFAwMTAgaXMgYSBwbGFuYXIgNDoyOjAgWVVWIHdpdGggaW50ZXJsZWF2ZWQgVVYgcGxhbmUs IDEwIGJpdHMKPiA+PiBwZXIgY2hhbm5lbCB2aWRlbyBmb3JtYXQuIFJvY2tjaGlwJ3Mgdm9wIHN1 cHBvcnQgdGhpcwo+ID4+IHZpZGVvIGZvcm1hdChsaXR0bGUgZW5kaWFuIG9ubHkpIGFzIHRoZSBp bnB1dCB2aWRlbyBmb3JtYXQuCj4gPj4KPiA+PiBTaWduZWQtb2ZmLWJ5OiBSYW5keSBMaSA8YXlh a2FAc291bGlrLmluZm8+Cj4gPj4gLS0tCj4gPj4gICBpbmNsdWRlL3VhcGkvZHJtL2RybV9mb3Vy Y2MuaCB8IDEgKwo+ID4+ICAgMSBmaWxlIGNoYW5nZWQsIDEgaW5zZXJ0aW9uKCspCj4gPj4KPiA+ PiBkaWZmIC0tZ2l0IGEvaW5jbHVkZS91YXBpL2RybS9kcm1fZm91cmNjLmggYi9pbmNsdWRlL3Vh cGkvZHJtL2RybV9mb3VyY2MuaAo+ID4+IGluZGV4IDllMWJiN2YuLmQyNzIxZGEgMTAwNjQ0Cj4g Pj4gLS0tIGEvaW5jbHVkZS91YXBpL2RybS9kcm1fZm91cmNjLmgKPiA+PiArKysgYi9pbmNsdWRl L3VhcGkvZHJtL2RybV9mb3VyY2MuaAo+ID4+IEBAIC0xMTksNiArMTE5LDcgQEAgZXh0ZXJuICJD IiB7Cj4gPj4gICAjZGVmaW5lIERSTV9GT1JNQVRfTlY2MQkJZm91cmNjX2NvZGUoJ04nLCAnVics ICc2JywgJzEnKSAvKiAyeDEgc3Vic2FtcGxlZCBDYjpDciBwbGFuZSAqLwo+ID4+ICAgI2RlZmlu ZSBEUk1fRk9STUFUX05WMjQJCWZvdXJjY19jb2RlKCdOJywgJ1YnLCAnMicsICc0JykgLyogbm9u LXN1YnNhbXBsZWQgQ3I6Q2IgcGxhbmUgKi8KPiA+PiAgICNkZWZpbmUgRFJNX0ZPUk1BVF9OVjQy CQlmb3VyY2NfY29kZSgnTicsICdWJywgJzQnLCAnMicpIC8qIG5vbi1zdWJzYW1wbGVkIENiOkNy IHBsYW5lICovCj4gPj4gKyNkZWZpbmUgRFJNX0ZPUk1BVF9QMDEwCQlmb3VyY2NfY29kZSgnUCcs ICcwJywgJzEnLCAnMCcpIC8qIDJ4MiBzdWJzYW1wbGVkIENyOkNiIHBsYW5lIDEwIGJpdHMgcGVy IGNoYW5uZWwgKi8KPiA+IFdlIGNvdWxkIHVzZSBhIGJldHRlciBkZXNjcmlwdGlvbiBvZiB0aGUg Zm9ybWF0IGhlcmUuIElJUkMgdGhlcmUgaXMKPiA+IDEwYml0cyBvZiBhY3R1YWwgZGF0YSBjb250 YWluZWQgaW4gZWFjaCAxNmJpdHMuIFNvIHRoZXJlIHNob3VsZCBiZSBhCj4gPiBwcm9wZXIgY29t bWVudCBleHBsYW5pbmcgaW4gd2hpY2ggd2F5IHRoZSBiaXRzIGFyZSBzdG9yZWQuCj4gSXQgaXMg YSBsaXR0bGUgaGFyZCB0byBkZXNjcmliZSBQMDEwLAoKLyoKICogMiBwbGFuZSBZQ2JDcgogKiBp bmRleCAwID0gWSBwbGFuZSwgWzE1OjBdIFk6WCAxMDo2IGxpdHRsZS1lbmRpYW4KICogaW5kZXgg MSA9IENyOkNiIHBsYW5lLCBbMzE6MF0gQ3I6WDpDYjpYIDEwOjY6MTA6NiBsaXR0bGUtZW5kaWFu CiAqLwoKLyoKICogMiBwbGFuZSBZQ2JDcgogKiBpbmRleCAwID0gWSBwbGFuZSwgWzE1OjBdIFkg MTYgbGl0dGxlLWVuZGlhbgogKiBpbmRleCAxID0gQ3I6Q2IgcGxhbmUsIFszMTowXSBDcjpDYiAx NjoxNiBsaXR0bGUtZW5kaWFuCiAqLwoKb3Igc29tZXRoaW5nIGxpa2UgdGhhdCAobm90IDEwMCUg c3VyZSBJIGdvdCB0aGUgb3JkZXIgb2YgYml0cyBhbmQKd2hhdG5vdCBjb3JyZWN0KS4KCi0tIApW aWxsZSBTeXJqw6Rsw6QKSW50ZWwgT1RDCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZy ZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3Rp bmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mga06.intel.com ([134.134.136.31]:26758 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1761063AbdADQq6 (ORCPT ); Wed, 4 Jan 2017 11:46:58 -0500 Date: Wed, 4 Jan 2017 18:46:49 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: ayaka Cc: dri-devel@lists.freedesktop.org, randy.li@rock-chips.com, linux-kernel@vger.kernel.org, daniel.vetter@intel.com, mchehab@kernel.org, linux-media@vger.kernel.org Subject: Re: [PATCH 1/2] drm_fourcc: Add new P010 video format Message-ID: <20170104164649.GL31595@intel.com> References: <1483347004-32593-1-git-send-email-ayaka@soulik.info> <1483347004-32593-2-git-send-email-ayaka@soulik.info> <20170104155632.GI31595@intel.com> <1f0969b0-31b3-f9ee-653e-3689fe27932d@soulik.info> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1f0969b0-31b3-f9ee-653e-3689fe27932d@soulik.info> Sender: linux-media-owner@vger.kernel.org List-ID: On Thu, Jan 05, 2017 at 12:31:27AM +0800, ayaka wrote: > > > On 01/04/2017 11:56 PM, Ville Syrjälä wrote: > > On Mon, Jan 02, 2017 at 04:50:03PM +0800, Randy Li wrote: > >> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits > >> per channel video format. Rockchip's vop support this > >> video format(little endian only) as the input video format. > >> > >> Signed-off-by: Randy Li > >> --- > >> include/uapi/drm/drm_fourcc.h | 1 + > >> 1 file changed, 1 insertion(+) > >> > >> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > >> index 9e1bb7f..d2721da 100644 > >> --- a/include/uapi/drm/drm_fourcc.h > >> +++ b/include/uapi/drm/drm_fourcc.h > >> @@ -119,6 +119,7 @@ extern "C" { > >> #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ > >> #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ > >> #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ > >> +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ > > We could use a better description of the format here. IIRC there is > > 10bits of actual data contained in each 16bits. So there should be a > > proper comment explaning in which way the bits are stored. > It is a little hard to describe P010, /* * 2 plane YCbCr * index 0 = Y plane, [15:0] Y:X 10:6 little-endian * index 1 = Cr:Cb plane, [31:0] Cr:X:Cb:X 10:6:10:6 little-endian */ /* * 2 plane YCbCr * index 0 = Y plane, [15:0] Y 16 little-endian * index 1 = Cr:Cb plane, [31:0] Cr:Cb 16:16 little-endian */ or something like that (not 100% sure I got the order of bits and whatnot correct). -- Ville Syrjälä Intel OTC