From: "Kirill A. Shutemov" <kirill@shutemov.name>
To: Liang Li <liang.z.li@intel.com>
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
tglx@linutronix.de, mingo@redhat.com,
kirill.shutemov@linux.intel.com, dave.hansen@linux.intel.com,
guangrong.xiao@linux.intel.com, pbonzini@redhat.com,
rkrcmar@redhat.com
Subject: Re: [PATCH RFC 0/4] 5-level EPT
Date: Thu, 5 Jan 2017 16:26:58 +0300 [thread overview]
Message-ID: <20170105132658.GD17319@node.shutemov.name> (raw)
In-Reply-To: <1483003563-25847-1-git-send-email-liang.z.li@intel.com>
On Thu, Dec 29, 2016 at 05:25:59PM +0800, Liang Li wrote:
> x86-64 is currently limited physical address width to 46 bits, which
> can support 64 TiB of memory. Some vendors require to support more for
> some use case. Intel plans to extend the physical address width to
> 52 bits in some of the future products.
>
> The current EPT implementation only supports 4 level page table, which
> can support maximum 48 bits physical address width, so it's needed to
> extend the EPT to 5 level to support 52 bits physical address width.
>
> This patchset has been tested in the SIMICS environment for 5 level
> paging guest, which was patched with Kirill's patchset for enabling
> 5 level page table, with both the EPT and shadow page support. I just
> covered the booting process, the guest can boot successfully.
>
> Some parts of this patchset can be improved. Any comments on the design
> or the patches would be appreciated.
This looks reasonable, assuming my very limited knowledge of the subject.
The first patch is actually in my patchset, split across two patches.
--
Kirill A. Shutemov
prev parent reply other threads:[~2017-01-05 13:34 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-29 9:25 [PATCH RFC 0/4] 5-level EPT Liang Li
2016-12-29 9:26 ` [PATCH RFC 1/4] x86: Add the new CPUID and CR4 bits for 5 level page table Liang Li
2016-12-29 9:26 ` [PATCH RFC 2/4] KVM: MMU: Rename PT64_ROOT_LEVEL to PT64_ROOT_4LEVEL Liang Li
2017-03-09 14:39 ` Paolo Bonzini
2016-12-29 9:26 ` [PATCH RFC 3/4] KVM: MMU: Add 5 level EPT & Shadow page table support Liang Li
2017-03-09 15:12 ` Paolo Bonzini
2016-12-29 9:26 ` [PATCH RFC 4/4] VMX: Expose the LA57 feature to VM Liang Li
2017-03-09 15:16 ` Paolo Bonzini
2016-12-29 20:38 ` [PATCH RFC 0/4] 5-level EPT Valdis.Kletnieks
2016-12-30 1:26 ` Li, Liang Z
2017-01-02 10:18 ` Paolo Bonzini
2017-01-17 2:18 ` Li, Liang Z
2017-03-09 14:16 ` Paolo Bonzini
2017-03-10 8:00 ` Yu Zhang
2017-01-05 13:26 ` Kirill A. Shutemov [this message]
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