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From: Jim Bride <jim.bride@linux.intel.com>
To: vathsala nagaraju <vathsala.nagaraju@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
	Patil Deepti <deepti.patil@intel.com>,
	dri-devel@lists.freedesktop.org,
	Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH 07/10] drm/i915/psr: set PSR_MASK bits for deep sleep
Date: Thu, 5 Jan 2017 12:40:33 -0800	[thread overview]
Message-ID: <20170105204033.GC2898@shiv> (raw)
In-Reply-To: <1483462671-13644-1-git-send-email-vathsala.nagaraju@intel.com>

On Tue, Jan 03, 2017 at 10:27:51PM +0530, vathsala nagaraju wrote:
> Program EDP_PSR_DEBUG_CTL (PSR_MASK) to enable system
> to go to deep sleep while in psr2.PSR2_STATUS bit 31:28
> should report value 8 , if system enters deep sleep state.
> 
> Also, EDP_FRAMES_BEFORE_SU_ENTRY is set 1 , if not set,
> flickering is observed on psr2 panel.
> 
> v2: (Ilia Mirkin)
> - Remove duplicate bit definition 25:27
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Patil Deepti <deepti.patil@intel.com>

Reviewed-by: Jim Bride <jim.bride@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 10 +++++++---
>  drivers/gpu/drm/i915/intel_dp.c  |  1 -
>  drivers/gpu/drm/i915/intel_psr.c | 29 ++++++++++++++++++++---------
>  3 files changed, 27 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5ca506a..272a283 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3597,9 +3597,12 @@ enum {
>  #define   EDP_PSR_PERF_CNT_MASK		0xffffff
>  
>  #define EDP_PSR_DEBUG_CTL		_MMIO(dev_priv->psr_mmio_base + 0x60)
> -#define   EDP_PSR_DEBUG_MASK_LPSP	(1<<27)
> -#define   EDP_PSR_DEBUG_MASK_MEMUP	(1<<26)
> -#define   EDP_PSR_DEBUG_MASK_HPD	(1<<25)
> +#define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1<<28)
> +#define   EDP_PSR_DEBUG_MASK_LPSP              (1<<27)
> +#define   EDP_PSR_DEBUG_MASK_MEMUP             (1<<26)
> +#define   EDP_PSR_DEBUG_MASK_HPD               (1<<25)
> +#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1<<16)
> +#define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)
>  
>  #define EDP_PSR2_CTL			_MMIO(0x6f900)
>  #define   EDP_PSR2_ENABLE		(1<<31)
> @@ -3614,6 +3617,7 @@ enum {
>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
>  #define   EDP_PSR2_IDLE_MASK		0xf
> +#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
>  
>  #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
>  #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 9b313a3..0a10858 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3655,7 +3655,6 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
>  			dev_priv->psr.alpm =
>  				intel_dp_get_alpm_status(intel_dp);
>  		}
> -
>  	}
>  
>  	/* Read the eDP Display control capabilities registers */
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 2e75ef6..19cd4d7 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -339,7 +339,9 @@ static void hsw_enable_source_psr2(struct intel_dp *intel_dp)
>  	/* FIXME: selective update is probably totally broken because it doesn't
>  	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
>  	 * good enough. */
> -	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> +	val |= EDP_PSR2_ENABLE |
> +		EDP_SU_TRACK_ENABLE |
> +		EDP_FRAMES_BEFORE_SU_ENTRY;
>  
>  	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>  		val |= EDP_PSR2_TP2_TIME_2500;
> @@ -512,18 +514,27 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>  				dev_priv->psr.psr2_support = false;
>  			else
>  				skl_psr_setup_su_vsc(intel_dp);
> +				I915_WRITE(EDP_PSR_DEBUG_CTL,
> +					   EDP_PSR_DEBUG_MASK_MEMUP |
> +					   EDP_PSR_DEBUG_MASK_HPD |
> +					   EDP_PSR_DEBUG_MASK_LPSP |
> +					   EDP_PSR_DEBUG_MASK_MAX_SLEEP |
> +					   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
>  		} else {
>  			/* set up vsc header for psr1 */
>  			hsw_psr_setup_vsc(intel_dp);
> +			/*
> +			 * Per Spec: Avoid continuous PSR exit by masking MEMUP
> +			 * and HPD. also mask LPSP to avoid dependency on other
> +			 * drivers that might block runtime_pm besides
> +			 * preventing  other hw tracking issues now we can rely
> +			 * on frontbuffer tracking.
> +			 */
> +			I915_WRITE(EDP_PSR_DEBUG_CTL,
> +				   EDP_PSR_DEBUG_MASK_MEMUP |
> +				   EDP_PSR_DEBUG_MASK_HPD |
> +				   EDP_PSR_DEBUG_MASK_LPSP);
>  		}
> -		/*
> -		 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
> -		 * Also mask LPSP to avoid dependency on other drivers that
> -		 * might block runtime_pm besides preventing other hw tracking
> -		 * issues now we can rely on frontbuffer tracking.
> -		 */
> -		I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
> -			   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
>  
>  		/* Enable PSR on the panel */
>  		hsw_psr_enable_sink(intel_dp);
> -- 
> 1.9.1
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  reply	other threads:[~2017-01-05 20:40 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-03 16:57 [PATCH 07/10] drm/i915/psr: set PSR_MASK bits for deep sleep vathsala nagaraju
2017-01-05 20:40 ` Jim Bride [this message]
  -- strict thread matches above, loose matches on Subject: below --
2017-01-13  0:31 vathsala nagaraju
2017-01-11 15:24 vathsala nagaraju
2017-01-06 18:59 vathsala nagaraju
2017-01-06 16:31 vathsala nagaraju
2017-01-02 11:30 [PATCH 00/10] enable psr2 for idle_screen on y-cordinate panel vathsala nagaraju
2017-01-02 11:31 ` [PATCH 07/10] drm/i915/psr: set PSR_MASK bits for deep sleep vathsala nagaraju
2017-01-03 16:31   ` Ilia Mirkin
2016-12-30  5:25 [PATCH 00/10] enable psr2 for idle_screen on y-cordinate panel vathsala nagaraju
2016-12-30  5:25 ` [PATCH 07/10] drm/i915/psr: set PSR_MASK bits for deep sleep vathsala nagaraju

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