From: Eduardo Habkost <ehabkost@redhat.com>
To: qemu-devel@nongnu.org
Cc: libvir-list@redhat.com
Subject: [Qemu-devel] [PATCH 3/5] i386/kvm: Blacklist TSX on known broken hosts
Date: Sun, 8 Jan 2017 17:40:39 -0200 [thread overview]
Message-ID: <20170108194041.10908-4-ehabkost@redhat.com> (raw)
In-Reply-To: <20170108194041.10908-1-ehabkost@redhat.com>
Some Intel CPUs are known to have a broken TSX implementation. A
microcode update from Intel disabled TSX on those CPUs, but
GET_SUPPORTED_CPUID might be reporting it as supported if the
hosts were not updated yet.
Manually fixup the GET_SUPPORTED_CPUID data to ensure we will
never enable TSX when running on those hosts.
Reference:
* glibc commit 2702856bf45c82cf8e69f2064f5aa15c0ceb6359:
https://sourceware.org/git/?p=glibc.git;a=commit;h=2702856bf45c82cf8e69f2064f5aa15c0ceb6359
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/kvm.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 10a9cd8f7f..3e99512640 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -272,6 +272,19 @@ static int get_para_features(KVMState *s)
return features;
}
+static bool host_tsx_blacklisted(void)
+{
+ int family, model, stepping;\
+ char vendor[CPUID_VENDOR_SZ + 1];
+
+ host_vendor_fms(vendor, &family, &model, &stepping);
+
+ /* Check if we are running on a Haswell host known to have broken TSX */
+ return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
+ (family == 6) &&
+ ((model == 63 && stepping < 4) ||
+ model == 60 || model == 69 || model == 70);
+}
/* Returns the value for a specific register on the cpuid entry
*/
@@ -355,6 +368,10 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
}
} else if (function == 6 && reg == R_EAX) {
ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
+ } else if (function == 7 && index == 0 && reg == R_EBX) {
+ if (host_tsx_blacklisted()) {
+ ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
+ }
} else if (function == 0x80000001 && reg == R_EDX) {
/* On Intel, kvm returns cpuid according to the Intel spec,
* so add missing bits according to the AMD spec:
--
2.11.0.259.g40922b1
next prev parent reply other threads:[~2017-01-08 19:41 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-08 19:40 [Qemu-devel] [PATCH 0/5] Use non-blacklisted family/model/stepping for Haswell CPU model Eduardo Habkost
2017-01-08 19:40 ` [Qemu-devel] [PATCH 1/5] i386: Add explicit array size to x86_cpu_vendor_words2str() Eduardo Habkost
2017-01-08 19:40 ` [Qemu-devel] [PATCH 2/5] i386: host_vendor_fms() helper function Eduardo Habkost
2017-01-08 19:40 ` Eduardo Habkost [this message]
2017-01-08 19:40 ` [Qemu-devel] [PATCH 4/5] pc: Add 2.9 machine-types Eduardo Habkost
2017-01-09 12:21 ` Laszlo Ersek
2017-01-10 4:06 ` Michael S. Tsirkin
2017-01-12 12:35 ` Eduardo Habkost
2017-01-08 19:40 ` [Qemu-devel] [PATCH 5/5] i386: Change stepping of Haswell to non-blacklisted value Eduardo Habkost
2017-01-08 19:47 ` [Qemu-devel] [PATCH 0/5] Use non-blacklisted family/model/stepping for Haswell CPU model no-reply
2017-01-08 19:55 ` Eduardo Habkost
2017-01-09 11:35 ` Dr. David Alan Gilbert
2017-01-12 12:33 ` Eduardo Habkost
2017-01-12 12:38 ` Dr. David Alan Gilbert
2017-01-12 13:04 ` Eduardo Habkost
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