From mboxrd@z Thu Jan 1 00:00:00 1970 From: shawnguo@kernel.org (Shawn Guo) Date: Mon, 9 Jan 2017 22:23:46 +0800 Subject: [PATCH v3 3/3] drm: zte: add overlay plane support In-Reply-To: References: <1482979048-32037-1-git-send-email-shawnguo@kernel.org> <1482979048-32037-4-git-send-email-shawnguo@kernel.org> Message-ID: <20170109142345.GN20956@dragon> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Jan 05, 2017 at 02:26:30AM -0500, Sean Paul wrote: > > +static u32 zx_vl_get_fmt(uint32_t format) > > +{ > > + u32 val = 0; > > + > > + switch (format) { > > + case DRM_FORMAT_NV12: > > + val = VL_FMT_YUV420; > > + break; > > + case DRM_FORMAT_YUV420: > > + val = VL_YUV420_PLANAR | VL_FMT_YUV420; > > + break; > > + case DRM_FORMAT_YUYV: > > + val = VL_YUV422_YUYV | VL_FMT_YUV422; > > + break; > > + case DRM_FORMAT_YVYU: > > + val = VL_YUV422_YVYU | VL_FMT_YUV422; > > + break; > > + case DRM_FORMAT_UYVY: > > + val = VL_YUV422_UYVY | VL_FMT_YUV422; > > + break; > > + case DRM_FORMAT_VYUY: > > + val = VL_YUV422_VYUY | VL_FMT_YUV422; > > + break; > > + case DRM_FORMAT_YUV444: > > + val = VL_FMT_YUV444_8BIT; > > Minor nit: You could have eliminated val and just returned directly > from all of the cases. Seems like there are a few other functions this > is also true for. Okay. I will change zx_vl_get_fmt() and zx_vl_rsz_get_fmt() accordingly. > > > + break; > > + default: > > + WARN_ONCE(1, "invalid pixel format %d\n", format); > > + } > > + > > + return val; > > +} > > +static void zx_vl_rsz_setup(struct zx_plane *zplane, uint32_t format, > > + u32 src_w, u32 src_h, u32 dst_w, u32 dst_h) > > +{ > > + void __iomem *rsz = zplane->rsz; > > + u32 src_chroma_w = src_w; > > + u32 src_chroma_h = src_h; > > + u32 fmt; > > + > > + /* Set up source and destination resolution */ > > + zx_writel(rsz + RSZ_SRC_CFG, RSZ_VER(src_h - 1) | RSZ_HOR(src_w - 1)); > > + zx_writel(rsz + RSZ_DEST_CFG, RSZ_VER(dst_h - 1) | RSZ_HOR(dst_w - 1)); > > + > > + /* Configure data format for VL RSZ */ > > + fmt = zx_vl_rsz_get_fmt(format); > > + zx_writel_mask(rsz + RSZ_VL_CTRL_CFG, RSZ_VL_FMT_MASK, fmt); > > + > > + /* Calculate Chroma heigth and width */ > > s/heigth/height/ Thanks for spotting it. > > > + if (fmt == RSZ_VL_FMT_YCBCR420) { > > + src_chroma_w = src_w >> 1; > > + src_chroma_h = src_h >> 1; > > + } else if (fmt == RSZ_VL_FMT_YCBCR422) { > > + src_chroma_w = src_w >> 1; > > + } > > + > > + /* Set up Luma and Chroma step registers */ > > + zx_writel(rsz + RSZ_VL_LUMA_HOR, rsz_step_value(src_w, dst_w)); > > + zx_writel(rsz + RSZ_VL_LUMA_VER, rsz_step_value(src_h, dst_h)); > > + zx_writel(rsz + RSZ_VL_CHROMA_HOR, rsz_step_value(src_chroma_w, dst_w)); > > + zx_writel(rsz + RSZ_VL_CHROMA_VER, rsz_step_value(src_chroma_h, dst_h)); > > + > > + zx_vl_rsz_set_update(zplane); > > +} > > diff --git a/drivers/gpu/drm/zte/zx_vou.c b/drivers/gpu/drm/zte/zx_vou.c > > index 3fb4fc04e693..e832c2ec3156 100644 > > --- a/drivers/gpu/drm/zte/zx_vou.c > > +++ b/drivers/gpu/drm/zte/zx_vou.c > > @@ -84,6 +84,8 @@ struct zx_crtc_bits { > > struct zx_crtc { > > struct drm_crtc crtc; > > struct drm_plane *primary; > > + struct drm_plane *overlay_active[VL_NUM]; > > + unsigned int overlay_active_num; > > I don't think this belongs here. You can instead add an active (or > enabled) bool to the zx_plane struct and keep track of it via > atomic_plane_update/disable. This allows you to call > zx_plane_set_update unconditionally in the vou irq handler and check > active/enabled in zx_plane_set_update. It's a truly great suggestion. How did I not think of it :) The v4 is coming for that. Thanks a lot for the review effort, Sean. Shawn From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shawn Guo Subject: Re: [PATCH v3 3/3] drm: zte: add overlay plane support Date: Mon, 9 Jan 2017 22:23:46 +0800 Message-ID: <20170109142345.GN20956@dragon> References: <1482979048-32037-1-git-send-email-shawnguo@kernel.org> <1482979048-32037-4-git-send-email-shawnguo@kernel.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id BA510899E6 for ; Mon, 9 Jan 2017 14:24:21 +0000 (UTC) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Sean Paul Cc: Daniel Vetter , Baoyou Xie , dri-devel , Linux ARM Kernel , Jun Nie List-Id: dri-devel@lists.freedesktop.org T24gVGh1LCBKYW4gMDUsIDIwMTcgYXQgMDI6MjY6MzBBTSAtMDUwMCwgU2VhbiBQYXVsIHdyb3Rl Ogo+ID4gK3N0YXRpYyB1MzIgenhfdmxfZ2V0X2ZtdCh1aW50MzJfdCBmb3JtYXQpCj4gPiArewo+ ID4gKyAgICAgICB1MzIgdmFsID0gMDsKPiA+ICsKPiA+ICsgICAgICAgc3dpdGNoIChmb3JtYXQp IHsKPiA+ICsgICAgICAgY2FzZSBEUk1fRk9STUFUX05WMTI6Cj4gPiArICAgICAgICAgICAgICAg dmFsID0gVkxfRk1UX1lVVjQyMDsKPiA+ICsgICAgICAgICAgICAgICBicmVhazsKPiA+ICsgICAg ICAgY2FzZSBEUk1fRk9STUFUX1lVVjQyMDoKPiA+ICsgICAgICAgICAgICAgICB2YWwgPSBWTF9Z VVY0MjBfUExBTkFSIHwgVkxfRk1UX1lVVjQyMDsKPiA+ICsgICAgICAgICAgICAgICBicmVhazsK PiA+ICsgICAgICAgY2FzZSBEUk1fRk9STUFUX1lVWVY6Cj4gPiArICAgICAgICAgICAgICAgdmFs ID0gVkxfWVVWNDIyX1lVWVYgfCBWTF9GTVRfWVVWNDIyOwo+ID4gKyAgICAgICAgICAgICAgIGJy ZWFrOwo+ID4gKyAgICAgICBjYXNlIERSTV9GT1JNQVRfWVZZVToKPiA+ICsgICAgICAgICAgICAg ICB2YWwgPSBWTF9ZVVY0MjJfWVZZVSB8IFZMX0ZNVF9ZVVY0MjI7Cj4gPiArICAgICAgICAgICAg ICAgYnJlYWs7Cj4gPiArICAgICAgIGNhc2UgRFJNX0ZPUk1BVF9VWVZZOgo+ID4gKyAgICAgICAg ICAgICAgIHZhbCA9IFZMX1lVVjQyMl9VWVZZIHwgVkxfRk1UX1lVVjQyMjsKPiA+ICsgICAgICAg ICAgICAgICBicmVhazsKPiA+ICsgICAgICAgY2FzZSBEUk1fRk9STUFUX1ZZVVk6Cj4gPiArICAg ICAgICAgICAgICAgdmFsID0gVkxfWVVWNDIyX1ZZVVkgfCBWTF9GTVRfWVVWNDIyOwo+ID4gKyAg ICAgICAgICAgICAgIGJyZWFrOwo+ID4gKyAgICAgICBjYXNlIERSTV9GT1JNQVRfWVVWNDQ0Ogo+ ID4gKyAgICAgICAgICAgICAgIHZhbCA9IFZMX0ZNVF9ZVVY0NDRfOEJJVDsKPiAKPiBNaW5vciBu aXQ6IFlvdSBjb3VsZCBoYXZlIGVsaW1pbmF0ZWQgdmFsIGFuZCBqdXN0IHJldHVybmVkIGRpcmVj dGx5Cj4gZnJvbSBhbGwgb2YgdGhlIGNhc2VzLiBTZWVtcyBsaWtlIHRoZXJlIGFyZSBhIGZldyBv dGhlciBmdW5jdGlvbnMgdGhpcwo+IGlzIGFsc28gdHJ1ZSBmb3IuCgpPa2F5LiAgSSB3aWxsIGNo YW5nZSB6eF92bF9nZXRfZm10KCkgYW5kIHp4X3ZsX3Jzel9nZXRfZm10KCkKYWNjb3JkaW5nbHku Cgo+IAo+ID4gKyAgICAgICAgICAgICAgIGJyZWFrOwo+ID4gKyAgICAgICBkZWZhdWx0Ogo+ID4g KyAgICAgICAgICAgICAgIFdBUk5fT05DRSgxLCAiaW52YWxpZCBwaXhlbCBmb3JtYXQgJWRcbiIs IGZvcm1hdCk7Cj4gPiArICAgICAgIH0KPiA+ICsKPiA+ICsgICAgICAgcmV0dXJuIHZhbDsKPiA+ ICt9Cgo8c25pcD4KCj4gPiArc3RhdGljIHZvaWQgenhfdmxfcnN6X3NldHVwKHN0cnVjdCB6eF9w bGFuZSAqenBsYW5lLCB1aW50MzJfdCBmb3JtYXQsCj4gPiArICAgICAgICAgICAgICAgICAgICAg ICAgICAgdTMyIHNyY193LCB1MzIgc3JjX2gsIHUzMiBkc3RfdywgdTMyIGRzdF9oKQo+ID4gK3sK PiA+ICsgICAgICAgdm9pZCBfX2lvbWVtICpyc3ogPSB6cGxhbmUtPnJzejsKPiA+ICsgICAgICAg dTMyIHNyY19jaHJvbWFfdyA9IHNyY193Owo+ID4gKyAgICAgICB1MzIgc3JjX2Nocm9tYV9oID0g c3JjX2g7Cj4gPiArICAgICAgIHUzMiBmbXQ7Cj4gPiArCj4gPiArICAgICAgIC8qIFNldCB1cCBz b3VyY2UgYW5kIGRlc3RpbmF0aW9uIHJlc29sdXRpb24gKi8KPiA+ICsgICAgICAgenhfd3JpdGVs KHJzeiArIFJTWl9TUkNfQ0ZHLCBSU1pfVkVSKHNyY19oIC0gMSkgfCBSU1pfSE9SKHNyY193IC0g MSkpOwo+ID4gKyAgICAgICB6eF93cml0ZWwocnN6ICsgUlNaX0RFU1RfQ0ZHLCBSU1pfVkVSKGRz dF9oIC0gMSkgfCBSU1pfSE9SKGRzdF93IC0gMSkpOwo+ID4gKwo+ID4gKyAgICAgICAvKiBDb25m aWd1cmUgZGF0YSBmb3JtYXQgZm9yIFZMIFJTWiAqLwo+ID4gKyAgICAgICBmbXQgPSB6eF92bF9y c3pfZ2V0X2ZtdChmb3JtYXQpOwo+ID4gKyAgICAgICB6eF93cml0ZWxfbWFzayhyc3ogKyBSU1pf VkxfQ1RSTF9DRkcsIFJTWl9WTF9GTVRfTUFTSywgZm10KTsKPiA+ICsKPiA+ICsgICAgICAgLyog Q2FsY3VsYXRlIENocm9tYSBoZWlndGggYW5kIHdpZHRoICovCj4gCj4gcy9oZWlndGgvaGVpZ2h0 LwoKVGhhbmtzIGZvciBzcG90dGluZyBpdC4KCj4gCj4gPiArICAgICAgIGlmIChmbXQgPT0gUlNa X1ZMX0ZNVF9ZQ0JDUjQyMCkgewo+ID4gKyAgICAgICAgICAgICAgIHNyY19jaHJvbWFfdyA9IHNy Y193ID4+IDE7Cj4gPiArICAgICAgICAgICAgICAgc3JjX2Nocm9tYV9oID0gc3JjX2ggPj4gMTsK PiA+ICsgICAgICAgfSBlbHNlIGlmIChmbXQgPT0gUlNaX1ZMX0ZNVF9ZQ0JDUjQyMikgewo+ID4g KyAgICAgICAgICAgICAgIHNyY19jaHJvbWFfdyA9IHNyY193ID4+IDE7Cj4gPiArICAgICAgIH0K PiA+ICsKPiA+ICsgICAgICAgLyogU2V0IHVwIEx1bWEgYW5kIENocm9tYSBzdGVwIHJlZ2lzdGVy cyAqLwo+ID4gKyAgICAgICB6eF93cml0ZWwocnN6ICsgUlNaX1ZMX0xVTUFfSE9SLCByc3pfc3Rl cF92YWx1ZShzcmNfdywgZHN0X3cpKTsKPiA+ICsgICAgICAgenhfd3JpdGVsKHJzeiArIFJTWl9W TF9MVU1BX1ZFUiwgcnN6X3N0ZXBfdmFsdWUoc3JjX2gsIGRzdF9oKSk7Cj4gPiArICAgICAgIHp4 X3dyaXRlbChyc3ogKyBSU1pfVkxfQ0hST01BX0hPUiwgcnN6X3N0ZXBfdmFsdWUoc3JjX2Nocm9t YV93LCBkc3RfdykpOwo+ID4gKyAgICAgICB6eF93cml0ZWwocnN6ICsgUlNaX1ZMX0NIUk9NQV9W RVIsIHJzel9zdGVwX3ZhbHVlKHNyY19jaHJvbWFfaCwgZHN0X2gpKTsKPiA+ICsKPiA+ICsgICAg ICAgenhfdmxfcnN6X3NldF91cGRhdGUoenBsYW5lKTsKPiA+ICt9Cgo8c25pcD4KCj4gPiBkaWZm IC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL3p0ZS96eF92b3UuYyBiL2RyaXZlcnMvZ3B1L2RybS96 dGUvenhfdm91LmMKPiA+IGluZGV4IDNmYjRmYzA0ZTY5My4uZTgzMmMyZWMzMTU2IDEwMDY0NAo+ ID4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL3p0ZS96eF92b3UuYwo+ID4gKysrIGIvZHJpdmVycy9n cHUvZHJtL3p0ZS96eF92b3UuYwo+ID4gQEAgLTg0LDYgKzg0LDggQEAgc3RydWN0IHp4X2NydGNf Yml0cyB7Cj4gPiAgc3RydWN0IHp4X2NydGMgewo+ID4gICAgICAgICBzdHJ1Y3QgZHJtX2NydGMg Y3J0YzsKPiA+ICAgICAgICAgc3RydWN0IGRybV9wbGFuZSAqcHJpbWFyeTsKPiA+ICsgICAgICAg c3RydWN0IGRybV9wbGFuZSAqb3ZlcmxheV9hY3RpdmVbVkxfTlVNXTsKPiA+ICsgICAgICAgdW5z aWduZWQgaW50IG92ZXJsYXlfYWN0aXZlX251bTsKPiAKPiBJIGRvbid0IHRoaW5rIHRoaXMgYmVs b25ncyBoZXJlLiBZb3UgY2FuIGluc3RlYWQgYWRkIGFuIGFjdGl2ZSAob3IKPiBlbmFibGVkKSBi b29sIHRvIHRoZSB6eF9wbGFuZSBzdHJ1Y3QgYW5kIGtlZXAgdHJhY2sgb2YgaXQgdmlhCj4gYXRv bWljX3BsYW5lX3VwZGF0ZS9kaXNhYmxlLiBUaGlzIGFsbG93cyB5b3UgdG8gY2FsbAo+IHp4X3Bs YW5lX3NldF91cGRhdGUgdW5jb25kaXRpb25hbGx5IGluIHRoZSB2b3UgaXJxIGhhbmRsZXIgYW5k IGNoZWNrCj4gYWN0aXZlL2VuYWJsZWQgaW4genhfcGxhbmVfc2V0X3VwZGF0ZS4KCkl0J3MgYSB0 cnVseSBncmVhdCBzdWdnZXN0aW9uLiAgSG93IGRpZCBJIG5vdCB0aGluayBvZiBpdCA6KSAgVGhl IHY0IGlzCmNvbWluZyBmb3IgdGhhdC4KClRoYW5rcyBhIGxvdCBmb3IgdGhlIHJldmlldyBlZmZv cnQsIFNlYW4uCgpTaGF3bgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3Rv cC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmkt ZGV2ZWwK