From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: Re: [PATCH v6] drm: add fourcc codes for 16bit R and RG Date: Wed, 11 Jan 2017 07:44:05 -0800 Message-ID: <20170111154405.GA1916@mail.bwidawsk.net> References: <20170104182859.GM31595@intel.com> <20170104183855.3852-1-fernetmenta@kodi.tv> <20170105113708.GN31595@intel.com> <88b5d93d-40df-9c1a-666e-9a3431833f88@vodafone.de> <20170111150504.GK31595@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <20170111150504.GK31595@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Ville =?utf-8?B?U3lyasOkbMOk?= Cc: intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rainer Hochecker , fernetmenta@online.de List-Id: dri-devel@lists.freedesktop.org T24gMTctMDEtMTEgMTc6MDU6MDQsIFZpbGxlIFN5cmrDpGzDpCB3cm90ZToKPk9uIFRodSwgSmFu IDA1LCAyMDE3IGF0IDAyOjQ1OjM3UE0gKzAxMDAsIENocmlzdGlhbiBLw7ZuaWcgd3JvdGU6Cj4+ IEFtIDA1LjAxLjIwMTcgdW0gMTI6Mzcgc2NocmllYiBWaWxsZSBTeXJqw6Rsw6Q6Cj4+ID4gT24g V2VkLCBKYW4gMDQsIDIwMTcgYXQgMDc6Mzg6NTVQTSArMDEwMCwgUmFpbmVyIEhvY2hlY2tlciB3 cm90ZToKPj4gPj4gRnJvbTogUmFpbmVyIEhvY2hlY2tlciA8ZmVybmV0bWVudGFAb25saW5lLmRl Pgo+PiA+Pgo+PiA+PiBUaGlzIGFkZHMgZm91cmNjIGNvZGVzIGZvciAxNmJpdCBwbGFuZXMgcmVx dWlyZWQgZm9yIERSTSBidWZmZXIKPj4gPj4gZXhwb3J0IHRvIG1lc2EuCj4+ID4+Cj4+ID4+IFNp Z25lZC1vZmYtYnk6IFJhaW5lciBIb2NoZWNrZXIgPGZlcm5ldG1lbnRhQG9ubGluZS5kZT4KPj4g PiBSZXZpZXdlZC1ieTogVmlsbGUgU3lyasOkbMOkIDx2aWxsZS5zeXJqYWxhQGxpbnV4LmludGVs LmNvbT4KPj4KPj4gR29vZCB0byBzZWUgc29tZSB3b3JrIGxhbmRpbmcgb24gdGhhdCBwYXJ0LCBw YXRjaCBpcyBBY2tlZC1ieTogQ2hyaXN0aWFuCj4+IEvDtm5pZyA8Y2hyaXN0aWFuLmtvZW5pZ0Bh bWQuY29tPi4KPgo+SGFzIHRoZSB1c2Vyc3BhY2Ugc2lkZSBvZiB0aGlzIGJlZW4gcmV2aWV3ZWQg YWxyZWFkeT8KPgo+L21lIHdvbmRlcnMgaWYgaXQncyBzYWZlIHRvIHB1c2ggdGhpcy4uLgo+CgpJ IGFja2VkIHRoZSBtZXNhIHNpZGUsIGFuZCBSYWluZXIgc2VudCBhIHZlcnNpb24gMiB3aGljaCBh bHNvIGxvb2tlZCBmaW5lIHRvIG1lLgpMZXQgbWUgYnVtcCB0aGF0IHRocmVhZC4uLgoKPj4KPj4g Pgo+PiA+PiAtLS0KPj4gPj4gICBpbmNsdWRlL3VhcGkvZHJtL2RybV9mb3VyY2MuaCB8IDcgKysr KysrKwo+PiA+PiAgIDEgZmlsZSBjaGFuZ2VkLCA3IGluc2VydGlvbnMoKykKPj4gPj4KPj4gPj4g ZGlmZiAtLWdpdCBhL2luY2x1ZGUvdWFwaS9kcm0vZHJtX2ZvdXJjYy5oIGIvaW5jbHVkZS91YXBp L2RybS9kcm1fZm91cmNjLmgKPj4gPj4gaW5kZXggYTU4OTBiZi4uZDIzMGU1OCAxMDA2NDQKPj4g Pj4gLS0tIGEvaW5jbHVkZS91YXBpL2RybS9kcm1fZm91cmNjLmgKPj4gPj4gKysrIGIvaW5jbHVk ZS91YXBpL2RybS9kcm1fZm91cmNjLmgKPj4gPj4gQEAgLTQxLDEwICs0MSwxNyBAQCBleHRlcm4g IkMiIHsKPj4gPj4gICAvKiA4IGJwcCBSZWQgKi8KPj4gPj4gICAjZGVmaW5lIERSTV9GT1JNQVRf UjgJCWZvdXJjY19jb2RlKCdSJywgJzgnLCAnICcsICcgJykgLyogWzc6MF0gUiAqLwo+PiA+Pgo+ PiA+PiArLyogMTYgYnBwIFJlZCAqLwo+PiA+PiArI2RlZmluZSBEUk1fRk9STUFUX1IxNgkJZm91 cmNjX2NvZGUoJ1InLCAnMScsICc2JywgJyAnKSAvKiBbMTU6MF0gUiBsaXR0bGUgZW5kaWFuICov Cj4+ID4+ICsKPj4gPj4gICAvKiAxNiBicHAgUkcgKi8KPj4gPj4gICAjZGVmaW5lIERSTV9GT1JN QVRfUkc4OAkJZm91cmNjX2NvZGUoJ1InLCAnRycsICc4JywgJzgnKSAvKiBbMTU6MF0gUjpHIDg6 OCBsaXR0bGUgZW5kaWFuICovCj4+ID4+ICAgI2RlZmluZSBEUk1fRk9STUFUX0dSODgJCWZvdXJj Y19jb2RlKCdHJywgJ1InLCAnOCcsICc4JykgLyogWzE1OjBdIEc6UiA4OjggbGl0dGxlIGVuZGlh biAqLwo+PiA+Pgo+PiA+PiArLyogMzIgYnBwIFJHICovCj4+ID4+ICsjZGVmaW5lIERSTV9GT1JN QVRfUkcxNjE2CWZvdXJjY19jb2RlKCdSJywgJ0cnLCAnMycsICcyJykgLyogWzMxOjBdIFI6RyAx NjoxNiBsaXR0bGUgZW5kaWFuICovCj4+ID4+ICsjZGVmaW5lIERSTV9GT1JNQVRfR1IxNjE2CWZv dXJjY19jb2RlKCdHJywgJ1InLCAnMycsICcyJykgLyogWzMxOjBdIEc6UiAxNjoxNiBsaXR0bGUg ZW5kaWFuICovCj4+ID4+ICsKPj4gPj4gICAvKiA4IGJwcCBSR0IgKi8KPj4gPj4gICAjZGVmaW5l IERSTV9GT1JNQVRfUkdCMzMyCWZvdXJjY19jb2RlKCdSJywgJ0cnLCAnQicsICc4JykgLyogWzc6 MF0gUjpHOkIgMzozOjIgKi8KPj4gPj4gICAjZGVmaW5lIERSTV9GT1JNQVRfQkdSMjMzCWZvdXJj Y19jb2RlKCdCJywgJ0cnLCAnUicsICc4JykgLyogWzc6MF0gQjpHOlIgMjozOjMgKi8KPj4gPj4g LS0KPj4gPj4gMi45LjMKPj4KPgo+LS0gCj5WaWxsZSBTeXJqw6Rsw6QKPkludGVsIE9UQwpfX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFp bGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5m cmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S938395AbdAKPv5 (ORCPT ); Wed, 11 Jan 2017 10:51:57 -0500 Received: from zangief.bwidawsk.net ([107.170.211.233]:33760 "EHLO mail.bwidawsk.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752788AbdAKPvx (ORCPT ); Wed, 11 Jan 2017 10:51:53 -0500 X-Greylist: delayed 462 seconds by postgrey-1.27 at vger.kernel.org; Wed, 11 Jan 2017 10:51:53 EST X-Spam-ASN: Date: Wed, 11 Jan 2017 07:44:05 -0800 From: Ben Widawsky To: Ville =?utf-8?B?U3lyasOkbMOk?= Cc: Christian =?utf-8?B?S8O2bmln?= , Rainer Hochecker , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, fernetmenta@online.de Subject: Re: [PATCH v6] drm: add fourcc codes for 16bit R and RG Message-ID: <20170111154405.GA1916@mail.bwidawsk.net> References: <20170104182859.GM31595@intel.com> <20170104183855.3852-1-fernetmenta@kodi.tv> <20170105113708.GN31595@intel.com> <88b5d93d-40df-9c1a-666e-9a3431833f88@vodafone.de> <20170111150504.GK31595@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20170111150504.GK31595@intel.com> User-Agent: Mutt/1.7.2 (2016-11-26) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17-01-11 17:05:04, Ville Syrjälä wrote: >On Thu, Jan 05, 2017 at 02:45:37PM +0100, Christian König wrote: >> Am 05.01.2017 um 12:37 schrieb Ville Syrjälä: >> > On Wed, Jan 04, 2017 at 07:38:55PM +0100, Rainer Hochecker wrote: >> >> From: Rainer Hochecker >> >> >> >> This adds fourcc codes for 16bit planes required for DRM buffer >> >> export to mesa. >> >> >> >> Signed-off-by: Rainer Hochecker >> > Reviewed-by: Ville Syrjälä >> >> Good to see some work landing on that part, patch is Acked-by: Christian >> König . > >Has the userspace side of this been reviewed already? > >/me wonders if it's safe to push this... > I acked the mesa side, and Rainer sent a version 2 which also looked fine to me. Let me bump that thread... >> >> > >> >> --- >> >> include/uapi/drm/drm_fourcc.h | 7 +++++++ >> >> 1 file changed, 7 insertions(+) >> >> >> >> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h >> >> index a5890bf..d230e58 100644 >> >> --- a/include/uapi/drm/drm_fourcc.h >> >> +++ b/include/uapi/drm/drm_fourcc.h >> >> @@ -41,10 +41,17 @@ extern "C" { >> >> /* 8 bpp Red */ >> >> #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ >> >> >> >> +/* 16 bpp Red */ >> >> +#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ >> >> + >> >> /* 16 bpp RG */ >> >> #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ >> >> #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ >> >> >> >> +/* 32 bpp RG */ >> >> +#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ >> >> +#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ >> >> + >> >> /* 8 bpp RGB */ >> >> #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ >> >> #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ >> >> -- >> >> 2.9.3 >> > >-- >Ville Syrjälä >Intel OTC