Re: [PATCH v2] PCI: rockchip: Add quirk to disable RC's ASPM L0s

[Brian Norris <briannorris@chromium.org>]

+ Heiko

On Wed, Jan 11, 2017 at 12:28:22PM -0600, Bjorn Helgaas wrote:
> On Mon, Dec 12, 2016 at 07:51:27PM +0800, Shawn Lin wrote:
> > diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> > index f2dca7b..35988fc 100644
> > --- a/drivers/pci/host/pcie-rockchip.c
> > +++ b/drivers/pci/host/pcie-rockchip.c
> > @@ -140,6 +140,8 @@
> >  #define   PCIE_RC_CONFIG_DCR_CSPL_SHIFT		18
> >  #define   PCIE_RC_CONFIG_DCR_CSPL_LIMIT		0xff
> >  #define   PCIE_RC_CONFIG_DCR_CPLS_SHIFT		26
> > +#define PCIE_RC_CONFIG_LINK_CAP		(PCIE_RC_CONFIG_BASE + 0xcc)
> > +#define   PCIE_RC_CONFIG_LINK_CAP_L0S		BIT(10)
> >  #define PCIE_RC_CONFIG_LCS		(PCIE_RC_CONFIG_BASE + 0xd0)
> >  #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
> >  #define PCIE_RC_CONFIG_THP_CAP		(PCIE_RC_CONFIG_BASE + 0x274)
> > @@ -653,6 +655,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> >  	status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK;
> >  	rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
> >  
> > +	/* Clear L0s from RC's link cap */
> > +	if (of_property_read_bool(dev->of_node, "apsm-no-l0s")) {
> 
> Did you test this?  This string ("apsm-no-l0s") doesn't match the
> "aspm-no-l0s" documented above.  The current tree doesn't contain either
> string in any DTS.

Ha, wow. FWIW in the tree I'm using, I have both this patch and a DTS
patch that uses the matching (but improperly-spelled) property. So *I*
have tested it. But I obviously didn't read it well enough. Or maybe I'm
mildly dyslexic?

Notably, Shawn sent a NON-matching DTS patch already here:

https://patchwork.kernel.org/patch/9477651/

So this definitely needs to get straightened out. Preferably by
s/apsm/aspm/ in this patch.

Regards,
Brian