diff for duplicates of <20170111200811.GA16865@uda0271908> diff --git a/a/1.txt b/N1/1.txt index 56aea4f..d47e982 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -3,29 +3,29 @@ On Thu, Jan 12, 2017 at 03:55:33AM +0800, Icenowy Zheng wrote: > > 11.01.2017, 04:24, "Bin Liu" <b-liu@ti.com>: > > On Tue, Jan 03, 2017 at 11:25:34PM +0800, Icenowy Zheng wrote: -> >> ?Lichee Pi Zero features a USB OTG port. +> >> Lichee Pi Zero features a USB OTG port. > >> -> >> ?Add support for it. +> >> Add support for it. > >> -> >> ?Note: in order to use the Host mode, the board must be powered via the -> >> ?+5V and GND pins. +> >> Note: in order to use the Host mode, the board must be powered via the +> >> +5V and GND pins. > >> -> >> ?Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> -> >> ?--- -> >> ??arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++ -> >> ??1 file changed, 10 insertions(+) +> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> +> >> --- +> >> arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++ +> >> 1 file changed, 10 insertions(+) > >> -> >> ?diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts -> >> ?index 0099affc6ce3..3d9168cbaeca 100644 -> >> ?--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts -> >> ?+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts -> >> ?@@ -71,3 +71,13 @@ -> >> ??????????pinctrl-names = "default"; -> >> ??????????status = "okay"; -> >> ??}; -> >> ?+ -> >> ?+&usb_otg { -> >> ?+ dr_mode = "otg"; +> >> diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts +> >> index 0099affc6ce3..3d9168cbaeca 100644 +> >> --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts +> >> +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts +> >> @@ -71,3 +71,13 @@ +> >> pinctrl-names = "default"; +> >> status = "okay"; +> >> }; +> >> + +> >> +&usb_otg { +> >> + dr_mode = "otg"; > > > > Why not set this default mode in dtsi instead? > > @@ -49,12 +49,12 @@ Regards, > (V3s itself has a CSI). > > > -> >> ?+ status = "okay"; -> >> ?+}; -> >> ?+ -> >> ?+&usbphy { -> >> ?+ usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>; -> >> ?+ status = "okay"; -> >> ?+}; -> >> ?-- -> >> ?2.11.0 +> >> + status = "okay"; +> >> +}; +> >> + +> >> +&usbphy { +> >> + usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>; +> >> + status = "okay"; +> >> +}; +> >> -- +> >> 2.11.0 diff --git a/a/content_digest b/N1/content_digest index 27548d5..5f006cd 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,10 +2,17 @@ "ref\020170103152534.20118-5-icenowy@aosc.xyz\0" "ref\020170110202443.GC2479@uda0271908\0" "ref\02733831484164533@web1g.yandex.ru\0" - "From\0b-liu@ti.com (Bin Liu)\0" - "Subject\0[PATCH 4/4] ARM: dts: sun8i: add OTG function to Lichee Pi Zero\0" + "From\0Bin Liu <b-liu@ti.com>\0" + "Subject\0Re: [PATCH 4/4] ARM: dts: sun8i: add OTG function to Lichee Pi Zero\0" "Date\0Wed, 11 Jan 2017 14:08:11 -0600\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Icenowy Zheng <icenowy@aosc.xyz>\0" + "Cc\0devicetree@vger.kernel.org <devicetree@vger.kernel.org>" + linux-usb@vger.kernel.org <linux-usb@vger.kernel.org> + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + Kishon Vijay Abraham I <kishon@ti.com> + Chen-Yu Tsai <wens@csie.org> + Maxime Ripard <maxime.ripard@free-electrons.com> + " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" "\00:1\0" "b\0" "On Thu, Jan 12, 2017 at 03:55:33AM +0800, Icenowy Zheng wrote:\n" @@ -13,29 +20,29 @@ "> \n" "> 11.01.2017, 04:24, \"Bin Liu\" <b-liu@ti.com>:\n" "> > On Tue, Jan 03, 2017 at 11:25:34PM +0800, Icenowy Zheng wrote:\n" - "> >> ?Lichee Pi Zero features a USB OTG port.\n" + "> >> \302\240Lichee Pi Zero features a USB OTG port.\n" "> >>\n" - "> >> ?Add support for it.\n" + "> >> \302\240Add support for it.\n" "> >>\n" - "> >> ?Note: in order to use the Host mode, the board must be powered via the\n" - "> >> ?+5V and GND pins.\n" + "> >> \302\240Note: in order to use the Host mode, the board must be powered via the\n" + "> >> \302\240+5V and GND pins.\n" "> >>\n" - "> >> ?Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>\n" - "> >> ?---\n" - "> >> ??arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++\n" - "> >> ??1 file changed, 10 insertions(+)\n" + "> >> \302\240Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>\n" + "> >> \302\240---\n" + "> >> \302\240\302\240arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++\n" + "> >> \302\240\302\2401 file changed, 10 insertions(+)\n" "> >>\n" - "> >> ?diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts\n" - "> >> ?index 0099affc6ce3..3d9168cbaeca 100644\n" - "> >> ?--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts\n" - "> >> ?+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts\n" - "> >> ?@@ -71,3 +71,13 @@\n" - "> >> ??????????pinctrl-names = \"default\";\n" - "> >> ??????????status = \"okay\";\n" - "> >> ??};\n" - "> >> ?+\n" - "> >> ?+&usb_otg {\n" - "> >> ?+ dr_mode = \"otg\";\n" + "> >> \302\240diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts\n" + "> >> \302\240index 0099affc6ce3..3d9168cbaeca 100644\n" + "> >> \302\240--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts\n" + "> >> \302\240+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts\n" + "> >> \302\240@@ -71,3 +71,13 @@\n" + "> >> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240pinctrl-names = \"default\";\n" + "> >> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240status = \"okay\";\n" + "> >> \302\240\302\240};\n" + "> >> \302\240+\n" + "> >> \302\240+&usb_otg {\n" + "> >> \302\240+ dr_mode = \"otg\";\n" "> >\n" "> > Why not set this default mode in dtsi instead?\n" "> >\n" @@ -59,14 +66,14 @@ "> (V3s itself has a CSI).\n" "> \n" "> >\n" - "> >> ?+ status = \"okay\";\n" - "> >> ?+};\n" - "> >> ?+\n" - "> >> ?+&usbphy {\n" - "> >> ?+ usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>;\n" - "> >> ?+ status = \"okay\";\n" - "> >> ?+};\n" - "> >> ?--\n" - > >> ?2.11.0 + "> >> \302\240+ status = \"okay\";\n" + "> >> \302\240+};\n" + "> >> \302\240+\n" + "> >> \302\240+&usbphy {\n" + "> >> \302\240+ usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>;\n" + "> >> \302\240+ status = \"okay\";\n" + "> >> \302\240+};\n" + "> >> \302\240--\n" + "> >> \302\2402.11.0" -c5329bd14678959b8e617fa139b064b1605cb872f91a75c26526f6238c7aa848 +0efb88d2141e2d08a1e309047941686f7a52196898c3068af9591511c0bf5e65
diff --git a/a/1.txt b/N2/1.txt index 56aea4f..d47e982 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -3,29 +3,29 @@ On Thu, Jan 12, 2017 at 03:55:33AM +0800, Icenowy Zheng wrote: > > 11.01.2017, 04:24, "Bin Liu" <b-liu@ti.com>: > > On Tue, Jan 03, 2017 at 11:25:34PM +0800, Icenowy Zheng wrote: -> >> ?Lichee Pi Zero features a USB OTG port. +> >> Lichee Pi Zero features a USB OTG port. > >> -> >> ?Add support for it. +> >> Add support for it. > >> -> >> ?Note: in order to use the Host mode, the board must be powered via the -> >> ?+5V and GND pins. +> >> Note: in order to use the Host mode, the board must be powered via the +> >> +5V and GND pins. > >> -> >> ?Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> -> >> ?--- -> >> ??arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++ -> >> ??1 file changed, 10 insertions(+) +> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> +> >> --- +> >> arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++ +> >> 1 file changed, 10 insertions(+) > >> -> >> ?diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts -> >> ?index 0099affc6ce3..3d9168cbaeca 100644 -> >> ?--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts -> >> ?+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts -> >> ?@@ -71,3 +71,13 @@ -> >> ??????????pinctrl-names = "default"; -> >> ??????????status = "okay"; -> >> ??}; -> >> ?+ -> >> ?+&usb_otg { -> >> ?+ dr_mode = "otg"; +> >> diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts +> >> index 0099affc6ce3..3d9168cbaeca 100644 +> >> --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts +> >> +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts +> >> @@ -71,3 +71,13 @@ +> >> pinctrl-names = "default"; +> >> status = "okay"; +> >> }; +> >> + +> >> +&usb_otg { +> >> + dr_mode = "otg"; > > > > Why not set this default mode in dtsi instead? > > @@ -49,12 +49,12 @@ Regards, > (V3s itself has a CSI). > > > -> >> ?+ status = "okay"; -> >> ?+}; -> >> ?+ -> >> ?+&usbphy { -> >> ?+ usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>; -> >> ?+ status = "okay"; -> >> ?+}; -> >> ?-- -> >> ?2.11.0 +> >> + status = "okay"; +> >> +}; +> >> + +> >> +&usbphy { +> >> + usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>; +> >> + status = "okay"; +> >> +}; +> >> -- +> >> 2.11.0 diff --git a/a/content_digest b/N2/content_digest index 27548d5..b7d5135 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -2,10 +2,17 @@ "ref\020170103152534.20118-5-icenowy@aosc.xyz\0" "ref\020170110202443.GC2479@uda0271908\0" "ref\02733831484164533@web1g.yandex.ru\0" - "From\0b-liu@ti.com (Bin Liu)\0" - "Subject\0[PATCH 4/4] ARM: dts: sun8i: add OTG function to Lichee Pi Zero\0" + "From\0Bin Liu <b-liu@ti.com>\0" + "Subject\0Re: [PATCH 4/4] ARM: dts: sun8i: add OTG function to Lichee Pi Zero\0" "Date\0Wed, 11 Jan 2017 14:08:11 -0600\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Icenowy Zheng <icenowy@aosc.xyz>\0" + "Cc\0Maxime Ripard <maxime.ripard@free-electrons.com>" + Chen-Yu Tsai <wens@csie.org> + Kishon Vijay Abraham I <kishon@ti.com> + devicetree@vger.kernel.org <devicetree@vger.kernel.org> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + " linux-usb@vger.kernel.org <linux-usb@vger.kernel.org>\0" "\00:1\0" "b\0" "On Thu, Jan 12, 2017 at 03:55:33AM +0800, Icenowy Zheng wrote:\n" @@ -13,29 +20,29 @@ "> \n" "> 11.01.2017, 04:24, \"Bin Liu\" <b-liu@ti.com>:\n" "> > On Tue, Jan 03, 2017 at 11:25:34PM +0800, Icenowy Zheng wrote:\n" - "> >> ?Lichee Pi Zero features a USB OTG port.\n" + "> >> \302\240Lichee Pi Zero features a USB OTG port.\n" "> >>\n" - "> >> ?Add support for it.\n" + "> >> \302\240Add support for it.\n" "> >>\n" - "> >> ?Note: in order to use the Host mode, the board must be powered via the\n" - "> >> ?+5V and GND pins.\n" + "> >> \302\240Note: in order to use the Host mode, the board must be powered via the\n" + "> >> \302\240+5V and GND pins.\n" "> >>\n" - "> >> ?Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>\n" - "> >> ?---\n" - "> >> ??arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++\n" - "> >> ??1 file changed, 10 insertions(+)\n" + "> >> \302\240Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>\n" + "> >> \302\240---\n" + "> >> \302\240\302\240arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++\n" + "> >> \302\240\302\2401 file changed, 10 insertions(+)\n" "> >>\n" - "> >> ?diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts\n" - "> >> ?index 0099affc6ce3..3d9168cbaeca 100644\n" - "> >> ?--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts\n" - "> >> ?+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts\n" - "> >> ?@@ -71,3 +71,13 @@\n" - "> >> ??????????pinctrl-names = \"default\";\n" - "> >> ??????????status = \"okay\";\n" - "> >> ??};\n" - "> >> ?+\n" - "> >> ?+&usb_otg {\n" - "> >> ?+ dr_mode = \"otg\";\n" + "> >> \302\240diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts\n" + "> >> \302\240index 0099affc6ce3..3d9168cbaeca 100644\n" + "> >> \302\240--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts\n" + "> >> \302\240+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts\n" + "> >> \302\240@@ -71,3 +71,13 @@\n" + "> >> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240pinctrl-names = \"default\";\n" + "> >> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240status = \"okay\";\n" + "> >> \302\240\302\240};\n" + "> >> \302\240+\n" + "> >> \302\240+&usb_otg {\n" + "> >> \302\240+ dr_mode = \"otg\";\n" "> >\n" "> > Why not set this default mode in dtsi instead?\n" "> >\n" @@ -59,14 +66,14 @@ "> (V3s itself has a CSI).\n" "> \n" "> >\n" - "> >> ?+ status = \"okay\";\n" - "> >> ?+};\n" - "> >> ?+\n" - "> >> ?+&usbphy {\n" - "> >> ?+ usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>;\n" - "> >> ?+ status = \"okay\";\n" - "> >> ?+};\n" - "> >> ?--\n" - > >> ?2.11.0 + "> >> \302\240+ status = \"okay\";\n" + "> >> \302\240+};\n" + "> >> \302\240+\n" + "> >> \302\240+&usbphy {\n" + "> >> \302\240+ usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>;\n" + "> >> \302\240+ status = \"okay\";\n" + "> >> \302\240+};\n" + "> >> \302\240--\n" + "> >> \302\2402.11.0" -c5329bd14678959b8e617fa139b064b1605cb872f91a75c26526f6238c7aa848 +419b67efa38f835d9e4e48e8d9790b84c82cf782256eb9c6643c38cc494258af
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.