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[81.231.233.234]) by smtp.gmail.com with ESMTPSA id 98sm2239087ljb.37.2017.01.12.12.46.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 12 Jan 2017 12:46:14 -0800 (PST) Date: Thu, 12 Jan 2017 21:46:14 +0100 From: "Edgar E. Iglesias" To: Peter Maydell Message-ID: <20170112204613.GZ9606@toto> References: <1484073849-32666-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1484073849-32666-1-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:4010:c07::242 Subject: Re: [Qemu-arm] [PATCH 0/3] target/arm: Support EL1 AArch32 guest under AArch64 EL2 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: XP/qpzmL6/Io On Tue, Jan 10, 2017 at 06:44:06PM +0000, Peter Maydell wrote: > The GICv3 virt patchset is sufficient to run a 64-bit guest under > a 64-bit host kernel. To run 32-bit guests under the 64-bit host > you need a few more things: > * data aborts from AArch32 need to provide instruction syndrome info > to the hypervisor > * the AArch32 interrupt code needs to handle VIRQ and VFIQ > * we need a DBGVCR32_EL2 register, because Linux's EL2 code uses > it to context-switch AArch32 DBGVCR between guests > > This patchset sits on top of the gicv3-virt patchset and is > sufficient to run a Linux 32-bit guest under 64-bit Linux host. Cool stuff Peter, I didn't think we were this close for this to work! 32bit hypervisors would be cool too but I'm guessing there's quite a bit of work before that works... Cheers, Edgar > > Git branch with the whole lot: > https://git.linaro.org/people/peter.maydell/qemu-arm.git aarch32-guest > > > Peter Maydell (3): > target/arm: A32, T32: Create Instruction Syndromes for Data Aborts > target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32() > target/arm: Implement DBGVCR32_EL2 system register > > target/arm/helper.c | 21 +++++ > target/arm/translate.c | 213 ++++++++++++++++++++++++++++++++++++------------- > 2 files changed, 178 insertions(+), 56 deletions(-) > > -- > 2.7.4 > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53461) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cRmGN-0006xs-Hm for qemu-devel@nongnu.org; Thu, 12 Jan 2017 15:46:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cRmGM-0000iz-Hk for qemu-devel@nongnu.org; Thu, 12 Jan 2017 15:46:23 -0500 Date: Thu, 12 Jan 2017 21:46:14 +0100 From: "Edgar E. Iglesias" Message-ID: <20170112204613.GZ9606@toto> References: <1484073849-32666-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1484073849-32666-1-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH 0/3] target/arm: Support EL1 AArch32 guest under AArch64 EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org On Tue, Jan 10, 2017 at 06:44:06PM +0000, Peter Maydell wrote: > The GICv3 virt patchset is sufficient to run a 64-bit guest under > a 64-bit host kernel. To run 32-bit guests under the 64-bit host > you need a few more things: > * data aborts from AArch32 need to provide instruction syndrome info > to the hypervisor > * the AArch32 interrupt code needs to handle VIRQ and VFIQ > * we need a DBGVCR32_EL2 register, because Linux's EL2 code uses > it to context-switch AArch32 DBGVCR between guests > > This patchset sits on top of the gicv3-virt patchset and is > sufficient to run a Linux 32-bit guest under 64-bit Linux host. Cool stuff Peter, I didn't think we were this close for this to work! 32bit hypervisors would be cool too but I'm guessing there's quite a bit of work before that works... Cheers, Edgar > > Git branch with the whole lot: > https://git.linaro.org/people/peter.maydell/qemu-arm.git aarch32-guest > > > Peter Maydell (3): > target/arm: A32, T32: Create Instruction Syndromes for Data Aborts > target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32() > target/arm: Implement DBGVCR32_EL2 system register > > target/arm/helper.c | 21 +++++ > target/arm/translate.c | 213 ++++++++++++++++++++++++++++++++++++------------- > 2 files changed, 178 insertions(+), 56 deletions(-) > > -- > 2.7.4 >