From: Yi Sun <yi.y.sun@linux.intel.com>
To: Dario Faggioli <dario.faggioli@citrix.com>
Cc: wei.liu2@citrix.com, he.chen@linux.intel.com,
andrew.cooper3@citrix.com, konrad.wilk@oracle.com,
ian.jackson@eu.citrix.com, mengxu@cis.upenn.edu,
jbeulich@suse.com, chao.p.peng@linux.intel.com,
xen-devel@lists.xenproject.org
Subject: Re: [PATCH v5 01/24] docs: create L2 Cache Allocation Technology (CAT) feature document
Date: Thu, 19 Jan 2017 14:11:27 +0800 [thread overview]
Message-ID: <20170119061127.GW7435@yi.y.sun> (raw)
In-Reply-To: <1484730675.7492.66.camel@citrix.com>
On 17-01-18 10:11:15, Dario Faggioli wrote:
> On Wed, 2017-01-18 at 10:02 +0800, Yi Sun wrote:
> > This patch creates L2 CAT feature document in doc/features/.
> > It describes details of L2 CAT.
> >
> > Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> > ---
> >
> Hey,
>
> it is very very useful to put _RIGHT_HERE_ a summary of what changed,
> within, this patch, wrt the previous version.
>
> That helps reviewers quite a bit, especially in making sure that you
> hav considered and addressed comments made during the previous
> iterations.
>
I have resend the patches with summary of what changed. Please check.
Thanks!
Your comments for these patches will be recorded.
> > docs/features/intel_psr_l2_cat.pandoc | 347
> > ++++++++++++++++++++++++++++++++++
> > 1 file changed, 347 insertions(+)
> > create mode 100644 docs/features/intel_psr_l2_cat.pandoc
>
> > --- /dev/null
> > +++ b/docs/features/intel_psr_l2_cat.pandoc
> > +
> > +# User details
> > +
> > +* Feature Enabling:
> > +
> > + Add "psr=cat" to boot line parameter to enable all supported level
> > CAT
> > + features.
> > +
> > +* xl interfaces:
> > +
> > + 1. `psr-cat-show [OPTIONS] domain-id`:
> > +
> > + Show domain L2 or L3 CAT CBM.
> > +
> > + New option `-l` is added.
> > + `-l2`: Show cbm for L2 cache.
> > + `-l3`: Show cbm for L3 cache.
> > +
> > + If neither `-l2` nor `-l3` is given, show both of them. If any
> > one
> > + is not supported, will print error info.
> > +
> I actually think the best behavior would be:
> - if -lX is specified, and LX is not supported ==> print error;
Will return error for this case. But the error log is not accurate so far.
Will refine this. Thanks!
> - if no -l is specified ==> print info about the supported levels.
>
That is my bad. In fact, the l3 info will be shown if no -l is specified.
> (See comment on patch 21.)
>
> > +## The relationship between L2 CAT and L3 CAT/CDP
> > +
> > +L2 CAT is independent of L3 CAT/CDP, which means L2 CAT would be
> > enabled
> > +while L3 CAT/CDP is disabled, or L2 CAT and L3 CAT/CDP are all
> > enabled.
> > +
>
> I find 'would be enabled' and 'are all enabled' a bit confusing.
>
> Maybe: "which means L2 cat can be enabled while L3 CAT/CDP is disabled,
> or L2 CAT and L3 CAT/CDP can be all enabled"
>
> ?
Agree, thank you!
>
> Regards,
> Dario
> --
> <<This happens because I choose it to happen!>> (Raistlin Majere)
> -----------------------------------------------------------------
> Dario Faggioli, Ph.D, http://about.me/dario.faggioli
> Senior Software Engineer, Citrix Systems R&D Ltd., Cambridge (UK)
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next prev parent reply other threads:[~2017-01-19 6:11 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-18 2:02 [PATCH v5 00/24] Enable L2 Cache Allocation Technology & Refactor psr.c Yi Sun
2017-01-18 2:02 ` [PATCH v5 01/24] docs: create L2 Cache Allocation Technology (CAT) feature document Yi Sun
2017-01-18 9:11 ` Dario Faggioli
2017-01-18 9:37 ` Yi Sun
2017-01-19 6:11 ` Yi Sun [this message]
2017-01-18 2:02 ` [PATCH v5 02/24] x86: refactor psr: remove L3 CAT/CDP codes Yi Sun
2017-01-18 2:02 ` [PATCH v5 03/24] x86: refactor psr: implement main data structures Yi Sun
2017-01-18 2:02 ` [PATCH v5 04/24] x86: refactor psr: implement CPU init and free flow Yi Sun
2017-01-18 2:02 ` [PATCH v5 05/24] x86: refactor psr: implement Domain init/free and schedule flows Yi Sun
2017-01-18 2:02 ` [PATCH v5 06/24] x86: refactor psr: implement get hw info flow Yi Sun
2017-01-18 2:02 ` [PATCH v5 07/24] x86: refactor psr: implement get value flow Yi Sun
2017-01-18 2:02 ` [PATCH v5 08/24] x86: refactor psr: set value: implement framework Yi Sun
2017-01-18 2:02 ` [PATCH v5 09/24] x86: refactor psr: set value: assemble features value array Yi Sun
2017-01-18 2:02 ` [PATCH v5 10/24] x86: refactor psr: set value: implement cos finding flow Yi Sun
2017-01-18 2:02 ` [PATCH v5 11/24] x86: refactor psr: set value: implement cos id picking flow Yi Sun
2017-01-18 2:02 ` [PATCH v5 12/24] x86: refactor psr: set value: implement write msr flow Yi Sun
2017-01-18 2:02 ` [PATCH v5 13/24] x86: refactor psr: implement CPU init and free flow for CDP Yi Sun
2017-01-18 2:02 ` [PATCH v5 14/24] x86: refactor psr: implement get hw info " Yi Sun
2017-01-18 2:02 ` [PATCH v5 15/24] x86: refactor psr: implement get value " Yi Sun
2017-01-18 2:02 ` [PATCH v5 16/24] x86: refactor psr: implement set value callback functions " Yi Sun
2017-01-18 2:02 ` [PATCH v5 17/24] x86: L2 CAT: implement CPU init and free flow Yi Sun
2017-01-18 2:02 ` [PATCH v5 18/24] x86: L2 CAT: implement get hw info flow Yi Sun
2017-01-18 2:02 ` [PATCH v5 19/24] x86: L2 CAT: implement get value flow Yi Sun
2017-01-18 2:02 ` [PATCH v5 20/24] x86: L2 CAT: implement set " Yi Sun
2017-01-18 2:02 ` [PATCH v5 21/24] tools: L2 CAT: support get HW info for L2 CAT Yi Sun
2017-01-18 8:33 ` Dario Faggioli
2017-01-18 2:02 ` [PATCH v5 22/24] tools: L2 CAT: support show cbm " Yi Sun
2017-01-18 2:02 ` [PATCH v5 23/24] tools: L2 CAT: support set " Yi Sun
2017-01-18 8:51 ` Dario Faggioli
2017-01-18 2:02 ` [PATCH v5 24/24] docs: add L2 CAT description in docs Yi Sun
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