Re: [PATCH 1/6] drm/i915: Pass around gen to tile_height to special case gen2

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Thu, Jan 19, 2017 at 07:26:54PM +0000, Chris Wilson wrote:
> gen2 has a different tiling pattern, and a fixed tile_height. Pass
> along the gen so that we the computed tile_row is large enough to align
> with gen2 fences.
> 
> Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/i915_gem.c        |  3 ++-
>  drivers/gpu/drm/i915/i915_gem_object.h | 12 ++++++------
>  drivers/gpu/drm/i915/i915_gem_tiling.c |  2 +-
>  3 files changed, 9 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index b2f8ac1386a2..9412eba5e0a8 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1696,7 +1696,8 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
>  
>  static unsigned int tile_row_pages(struct drm_i915_gem_object *obj)
>  {
> -	return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT;
> +	int gen = INTEL_GEN(to_i915(obj->base.dev));
> +	return i915_gem_object_get_tile_row_size(obj, gen) >> PAGE_SHIFT;
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/i915_gem_object.h b/drivers/gpu/drm/i915/i915_gem_object.h
> index 290eaa7fc9eb..33a7d031e749 100644
> --- a/drivers/gpu/drm/i915/i915_gem_object.h
> +++ b/drivers/gpu/drm/i915/i915_gem_object.h
> @@ -318,23 +318,23 @@ i915_gem_object_get_stride(struct drm_i915_gem_object *obj)
>  }
>  
>  static inline unsigned int
> -i915_gem_tile_height(unsigned int tiling)
> +i915_gem_tile_height(int gen, unsigned int tiling)
>  {
>  	GEM_BUG_ON(!tiling);
> -	return tiling == I915_TILING_Y ? 32 : 8;
> +	return gen == 2 ? 16 : tiling == I915_TILING_Y ? 32 : 8;

Still inaccurate for 915+Y, but if this is only used to compute the tile
row size it'll just give a needlessly large answer and so should be
safe.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  }
>  
>  static inline unsigned int
> -i915_gem_object_get_tile_height(struct drm_i915_gem_object *obj)
> +i915_gem_object_get_tile_height(struct drm_i915_gem_object *obj, int gen)
>  {
> -	return i915_gem_tile_height(i915_gem_object_get_tiling(obj));
> +	return i915_gem_tile_height(gen, i915_gem_object_get_tiling(obj));
>  }
>  
>  static inline unsigned int
> -i915_gem_object_get_tile_row_size(struct drm_i915_gem_object *obj)
> +i915_gem_object_get_tile_row_size(struct drm_i915_gem_object *obj, int gen)
>  {
>  	return (i915_gem_object_get_stride(obj) *
> -		i915_gem_object_get_tile_height(obj));
> +		i915_gem_object_get_tile_height(obj, gen));
>  }
>  
>  int i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
> diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> index b1361cfd4c5c..bfa4a563ebf1 100644
> --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> @@ -81,7 +81,7 @@ u32 i915_gem_fence_size(struct drm_i915_private *i915,
>  	GEM_BUG_ON(!stride);
>  
>  	if (INTEL_GEN(i915) >= 4) {
> -		stride *= i915_gem_tile_height(tiling);
> +		stride *= i915_gem_tile_height(INTEL_GEN(i915), tiling);
>  		GEM_BUG_ON(!IS_ALIGNED(stride, I965_FENCE_PAGE));
>  		return roundup(size, stride);
>  	}
> -- 
> 2.11.0
> 
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-- 
Ville Syrjälä
Intel OTC
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