From mboxrd@z Thu Jan 1 00:00:00 1970 From: andrew@lunn.ch (Andrew Lunn) Date: Fri, 20 Jan 2017 01:06:45 +0100 Subject: [PATCH v5 1/2] net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >= num_of_ports In-Reply-To: <871svylmvb.fsf@weeman.i-did-not-set--mail-host-address--so-tickle-me> References: <20170119214934.27442-1-gregory.clement@free-electrons.com> <20170119214934.27442-2-gregory.clement@free-electrons.com> <871svylmvb.fsf@weeman.i-did-not-set--mail-host-address--so-tickle-me> Message-ID: <20170120000645.GA31483@lunn.ch> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Jan 19, 2017 at 05:13:12PM -0500, Vivien Didelot wrote: > Hi Gregory, > > Gregory CLEMENT writes: > > > From: Romain Perier > > > > Some Marvell ethernet switches have internal ethernet transceivers with > > hardcoded phy addresses. These addresses can be greater than the number > > of ports or its value might be different than the associated port number. > > This is for example the case for MV88E6341 that has 6 ports and internal > > Port 1 to Port4 PHYs mapped at SMI addresses from 0x11 to 0x14. > > Isn't there an hardware table used to map the PHY addresses on such chip? The 6390 has something like this. But if we can avoid it, lets keep it KISS. Andrew From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753787AbdATAHd (ORCPT ); Thu, 19 Jan 2017 19:07:33 -0500 Received: from vps0.lunn.ch ([178.209.37.122]:38916 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752936AbdATAHY (ORCPT ); Thu, 19 Jan 2017 19:07:24 -0500 Date: Fri, 20 Jan 2017 01:06:45 +0100 From: Andrew Lunn To: Vivien Didelot Cc: Gregory CLEMENT , Florian Fainelli , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, "David S. Miller" , Jason Cooper , Sebastian Hesselbarth , Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Nadav Haklai , Wilson Ding , Kostya Porotchkin , Joe Zhou , Jon Pannell Subject: Re: [PATCH v5 1/2] net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >= num_of_ports Message-ID: <20170120000645.GA31483@lunn.ch> References: <20170119214934.27442-1-gregory.clement@free-electrons.com> <20170119214934.27442-2-gregory.clement@free-electrons.com> <871svylmvb.fsf@weeman.i-did-not-set--mail-host-address--so-tickle-me> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <871svylmvb.fsf@weeman.i-did-not-set--mail-host-address--so-tickle-me> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 19, 2017 at 05:13:12PM -0500, Vivien Didelot wrote: > Hi Gregory, > > Gregory CLEMENT writes: > > > From: Romain Perier > > > > Some Marvell ethernet switches have internal ethernet transceivers with > > hardcoded phy addresses. These addresses can be greater than the number > > of ports or its value might be different than the associated port number. > > This is for example the case for MV88E6341 that has 6 ports and internal > > Port 1 to Port4 PHYs mapped at SMI addresses from 0x11 to 0x14. > > Isn't there an hardware table used to map the PHY addresses on such chip? The 6390 has something like this. But if we can avoid it, lets keep it KISS. Andrew From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Lunn Subject: Re: [PATCH v5 1/2] net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >= num_of_ports Date: Fri, 20 Jan 2017 01:06:45 +0100 Message-ID: <20170120000645.GA31483@lunn.ch> References: <20170119214934.27442-1-gregory.clement@free-electrons.com> <20170119214934.27442-2-gregory.clement@free-electrons.com> <871svylmvb.fsf@weeman.i-did-not-set--mail-host-address--so-tickle-me> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: Thomas Petazzoni , Florian Fainelli , Jason Cooper , Joe Zhou , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jon Pannell , Nadav Haklai , Kostya Porotchkin , Gregory CLEMENT , Wilson Ding , "David S. Miller" , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth To: Vivien Didelot Return-path: Content-Disposition: inline In-Reply-To: <871svylmvb.fsf@weeman.i-did-not-set--mail-host-address--so-tickle-me> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org List-Id: netdev.vger.kernel.org On Thu, Jan 19, 2017 at 05:13:12PM -0500, Vivien Didelot wrote: > Hi Gregory, > > Gregory CLEMENT writes: > > > From: Romain Perier > > > > Some Marvell ethernet switches have internal ethernet transceivers with > > hardcoded phy addresses. These addresses can be greater than the number > > of ports or its value might be different than the associated port number. > > This is for example the case for MV88E6341 that has 6 ports and internal > > Port 1 to Port4 PHYs mapped at SMI addresses from 0x11 to 0x14. > > Isn't there an hardware table used to map the PHY addresses on such chip? The 6390 has something like this. But if we can avoid it, lets keep it KISS. Andrew