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From: Nils Holland <nholland-iI9p2NPcQ/rYtjvyW6yDsg@public.gmane.org>
To: "Zhu, Rex" <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Cc: "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org"
	<amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Subject: Re: Bug (and probably, fix): UVD initialization / clock gating issue on kabini
Date: Mon, 23 Jan 2017 12:44:21 +0100	[thread overview]
Message-ID: <20170123114420.GA2254@tisys.org> (raw)
In-Reply-To: <CY4PR12MB1687C4749E80E440DE9C89C5FB720-rpdhrqHFk06Y0SjTqZDccQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>

On Mon, Jan 23, 2017 at 10:55:49AM +0000, Zhu, Rex wrote:
> we fixed this issue on Kv as uvd pg was enabled on APU.
> 
> We need to change the uvd cg mode.
> When idle, use hw cg. And encode, use sw cg.
> 
> So 
> WREG32(mmUVD_CGC_GATE, 0);  // ture off cg.
> Then 
> uvd_v4_2_set_dcm(adev, true);  // set sw cg.
> The first patch can fix this issue.
> 
> The second dpm patch can fix similar issue which caused by dpm's power state setting.

Ah, thanks, that sounds good! I'll give these two patches a try on my
system soon and report back in case I encounter any problems! :-)

Greetings
Nils
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      parent reply	other threads:[~2017-01-23 11:44 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-22 19:26 Bug: UVD initialization / clock gating issue on kabini Nils Holland
     [not found] ` <20170122192610.GB3125-iI9p2NPcQ/rYtjvyW6yDsg@public.gmane.org>
2017-01-23  0:47   ` Bug (and probably, fix): " Nils Holland
     [not found]     ` <20170123004738.GA2893-iI9p2NPcQ/rYtjvyW6yDsg@public.gmane.org>
2017-01-23 10:55       ` Zhu, Rex
     [not found]         ` <CY4PR12MB1687C4749E80E440DE9C89C5FB720-rpdhrqHFk06Y0SjTqZDccQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-01-23 11:44           ` Nils Holland [this message]

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