Re: [PATCH] drm/i915: Get correct display clock on 945gm

From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Arthur Heymans <arthur@aheymans.xyz>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Get correct display clock on 945gm
Date: Fri, 27 Jan 2017 18:57:19 +0200	[thread overview]
Message-ID: <20170127165719.GH31595@intel.com> (raw)
In-Reply-To: <87vat01mgd.fsf@aheymans.xyz>

On Fri, Jan 27, 2017 at 05:45:06PM +0100, Arthur Heymans wrote:
> Ville Syrjälä <ville.syrjala@linux.intel.com> writes:
> 
> > On Fri, Jan 27, 2017 at 03:44:27PM +0100, Arthur Heymans wrote:
> >
> > That indeed is what the docs say.
> >
> > The code is tantalizingly close to the 915gm code now, so maybe
> > we could share it with a simple
> >
> > if (IS_915GM(dev_priv))
> > 	return 320000;
> > else
> > 	return 333333;
> >
> 
> Agreed but it's the other way around ;)

Indeed. Apparently my brain can't reconcile the fact that the older part
is faster.

> 
> > Now if someone could figure out where to dig up the DDR and FSB clocks
> > we could also fix up the 190 vs. 200 MHz case...
> >
> >> +		default:
> >> +		case GC_DISPLAY_CLOCK_190_200_MHZ:
> >> +			return 200000;
> >> +		}
> >> +	}
> >> +}
> >> +
> 
> Hmm that seems to be 915gm specific (always 200 on 945gm). According to
> "Mobile Intel® 915/910 Express Chipset: Datasheet", the only fsb/dram
> combo that has 190MHz is FSB: 533MHz, DDR333. All the other supported
> combos have 200Mhz set by that configuration.

Yeah. Unfortunately I couldn't find a solid source of FSB/DDR clock
information in the spec, apart from the actual strap pins but I can't
see any register that would reflect those. So I guess we'll just leave
it the way it is.

-- 
Ville Syrjälä
Intel OTC
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