From mboxrd@z Thu Jan 1 00:00:00 1970 From: John Keeping Subject: [PATCH v3 15/24] drm/rockchip: dw-mipi-dsi: configure PHY before enabling Date: Sun, 29 Jan 2017 13:24:35 +0000 Message-ID: <20170129132444.25251-16-john@metanate.com> References: <20170129132444.25251-1-john@metanate.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20170129132444.25251-1-john@metanate.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Mark Yao Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Chris Zhong , linux-arm-kernel@lists.infradead.org List-Id: linux-rockchip.vger.kernel.org VGhlIGJpYXMsIGJhbmRnYXAgYW5kIFBMTCBzaG91bGQgYWxsIGJlIGNvbmZpZ3VyZWQgYmVmb3Jl IHdlIGVuYWJsZQp0aGVtLgoKU2lnbmVkLW9mZi1ieTogSm9obiBLZWVwaW5nIDxqb2huQG1ldGFu YXRlLmNvbT4KLS0tCnYzOgotIFNxdWFzaCB0b2dldGhlciB0d28gcGF0Y2hlcyB0aGF0IGJvdGgg YWZmZWN0IGluaXRpYWxpemF0aW9uIG9yZGVyIG9mCiAgdGhlIFBIWQpVbmNoYW5nZWQgaW4gdjIK CiBkcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvZHctbWlwaS1kc2kuYyB8IDExICsrKysrKy0tLS0t CiAxIGZpbGUgY2hhbmdlZCwgNiBpbnNlcnRpb25zKCspLCA1IGRlbGV0aW9ucygtKQoKZGlmZiAt LWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jIGIvZHJpdmVycy9n cHUvZHJtL3JvY2tjaGlwL2R3LW1pcGktZHNpLmMKaW5kZXggNWIzMDY4ZTllOGRiLi5jZmU3ZTRi YTMwNWMgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9kdy1taXBpLWRzaS5j CisrKyBiL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jCkBAIC00MTMsMTIg KzQxMywxNyBAQCBzdGF0aWMgaW50IGR3X21pcGlfZHNpX3BoeV9pbml0KHN0cnVjdCBkd19taXBp X2RzaSAqZHNpKQogCiAJZHdfbWlwaV9kc2lfcGh5X3dyaXRlKGRzaSwgMHg0NCwgSFNGUkVRUkFO R0VfU0VMKHRlc3RkaW4pKTsKIAotCWR3X21pcGlfZHNpX3BoeV93cml0ZShkc2ksIDB4MTksIFBM TF9MT09QX0RJVl9FTiB8IFBMTF9JTlBVVF9ESVZfRU4pOwogCWR3X21pcGlfZHNpX3BoeV93cml0 ZShkc2ksIDB4MTcsIElOUFVUX0RJVklERVIoZHNpLT5pbnB1dF9kaXYpKTsKIAlkd19taXBpX2Rz aV9waHlfd3JpdGUoZHNpLCAweDE4LCBMT09QX0RJVl9MT1dfU0VMKGRzaS0+ZmVlZGJhY2tfZGl2 KSB8CiAJCQkJCSBMT1dfUFJPR1JBTV9FTik7CiAJZHdfbWlwaV9kc2lfcGh5X3dyaXRlKGRzaSwg MHgxOCwgTE9PUF9ESVZfSElHSF9TRUwoZHNpLT5mZWVkYmFja19kaXYpIHwKIAkJCQkJIEhJR0hf UFJPR1JBTV9FTik7CisJZHdfbWlwaV9kc2lfcGh5X3dyaXRlKGRzaSwgMHgxOSwgUExMX0xPT1Bf RElWX0VOIHwgUExMX0lOUFVUX0RJVl9FTik7CisKKwlkd19taXBpX2RzaV9waHlfd3JpdGUoZHNp LCAweDIyLCBMT1dfUFJPR1JBTV9FTiB8CisJCQkJCSBCSUFTRVhUUl9TRUwoQklBU0VYVFJfMTI3 XzcpKTsKKwlkd19taXBpX2RzaV9waHlfd3JpdGUoZHNpLCAweDIyLCBISUdIX1BST0dSQU1fRU4g fAorCQkJCQkgQkFOREdBUF9TRUwoQkFOREdBUF85Nl8xMCkpOwogCiAJZHdfbWlwaV9kc2lfcGh5 X3dyaXRlKGRzaSwgMHgyMCwgUE9XRVJfQ09OVFJPTCB8IElOVEVSTkFMX1JFR19DVVJSRU5UIHwK IAkJCQkJIEJJQVNfQkxPQ0tfT04gfCBCQU5ER0FQX09OKTsKQEAgLTQyOSwxMCArNDM0LDYgQEAg c3RhdGljIGludCBkd19taXBpX2RzaV9waHlfaW5pdChzdHJ1Y3QgZHdfbWlwaV9kc2kgKmRzaSkK IAkJCQkJIFNFVFJEX01BWCB8IFBPV0VSX01BTkFHRSB8CiAJCQkJCSBURVJfUkVTSVNUT1JTX09O KTsKIAotCWR3X21pcGlfZHNpX3BoeV93cml0ZShkc2ksIDB4MjIsIExPV19QUk9HUkFNX0VOIHwK LQkJCQkJIEJJQVNFWFRSX1NFTChCSUFTRVhUUl8xMjdfNykpOwotCWR3X21pcGlfZHNpX3BoeV93 cml0ZShkc2ksIDB4MjIsIEhJR0hfUFJPR1JBTV9FTiB8Ci0JCQkJCSBCQU5ER0FQX1NFTChCQU5E R0FQXzk2XzEwKSk7CiAKIAlkd19taXBpX2RzaV9waHlfd3JpdGUoZHNpLCAweDcwLCBUTFBfUFJP R1JBTV9FTiB8IDB4Zik7CiAJZHdfbWlwaV9kc2lfcGh5X3dyaXRlKGRzaSwgMHg3MSwgVEhTX1BS RV9QUk9HUkFNX0VOIHwgMHg1NSk7Ci0tIAoyLjExLjAuMTk3LmdiNTU2ZGU1LmRpcnR5CgpfX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFp bGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5m cmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 From: john@metanate.com (John Keeping) Date: Sun, 29 Jan 2017 13:24:35 +0000 Subject: [PATCH v3 15/24] drm/rockchip: dw-mipi-dsi: configure PHY before enabling In-Reply-To: <20170129132444.25251-1-john@metanate.com> References: <20170129132444.25251-1-john@metanate.com> Message-ID: <20170129132444.25251-16-john@metanate.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org The bias, bandgap and PLL should all be configured before we enable them. Signed-off-by: John Keeping --- v3: - Squash together two patches that both affect initialization order of the PHY Unchanged in v2 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index 5b3068e9e8db..cfe7e4ba305c 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -413,12 +413,17 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin)); - dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div)); dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) | LOW_PROGRAM_EN); dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) | HIGH_PROGRAM_EN); + dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); + + dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN | + BIASEXTR_SEL(BIASEXTR_127_7)); + dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN | + BANDGAP_SEL(BANDGAP_96_10)); dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT | BIAS_BLOCK_ON | BANDGAP_ON); @@ -429,10 +434,6 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) SETRD_MAX | POWER_MANAGE | TER_RESISTORS_ON); - dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN | - BIASEXTR_SEL(BIASEXTR_127_7)); - dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN | - BANDGAP_SEL(BANDGAP_96_10)); dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf); dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55); -- 2.11.0.197.gb556de5.dirty From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751736AbdA2Os0 (ORCPT ); Sun, 29 Jan 2017 09:48:26 -0500 Received: from dougal.metanate.com ([90.155.101.14]:14382 "EHLO metanate.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751626AbdA2OsK (ORCPT ); Sun, 29 Jan 2017 09:48:10 -0500 From: John Keeping To: Mark Yao Cc: Chris Zhong , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, John Keeping Subject: [PATCH v3 15/24] drm/rockchip: dw-mipi-dsi: configure PHY before enabling Date: Sun, 29 Jan 2017 13:24:35 +0000 Message-Id: <20170129132444.25251-16-john@metanate.com> X-Mailer: git-send-email 2.11.0.197.gb556de5.dirty In-Reply-To: <20170129132444.25251-1-john@metanate.com> References: <20170129132444.25251-1-john@metanate.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The bias, bandgap and PLL should all be configured before we enable them. Signed-off-by: John Keeping --- v3: - Squash together two patches that both affect initialization order of the PHY Unchanged in v2 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index 5b3068e9e8db..cfe7e4ba305c 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -413,12 +413,17 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin)); - dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div)); dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) | LOW_PROGRAM_EN); dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) | HIGH_PROGRAM_EN); + dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); + + dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN | + BIASEXTR_SEL(BIASEXTR_127_7)); + dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN | + BANDGAP_SEL(BANDGAP_96_10)); dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT | BIAS_BLOCK_ON | BANDGAP_ON); @@ -429,10 +434,6 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) SETRD_MAX | POWER_MANAGE | TER_RESISTORS_ON); - dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN | - BIASEXTR_SEL(BIASEXTR_127_7)); - dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN | - BANDGAP_SEL(BANDGAP_96_10)); dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf); dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55); -- 2.11.0.197.gb556de5.dirty