From mboxrd@z Thu Jan 1 00:00:00 1970 From: John Keeping Subject: [PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL configuration Date: Sun, 29 Jan 2017 13:24:37 +0000 Message-ID: <20170129132444.25251-18-john@metanate.com> References: <20170129132444.25251-1-john@metanate.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20170129132444.25251-1-john@metanate.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Mark Yao Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Chris Zhong , linux-arm-kernel@lists.infradead.org List-Id: linux-rockchip.vger.kernel.org VGhlIG11bHRpcGxpY2F0aW9uIHJhdGlvIGZvciB0aGUgUExMIGlzIHJlcXVpcmVkIHRvIGJlIGV2 ZW4gZHVlIHRvIHRoZQp1c2Ugb2YgYSAiYnkgMiBwcmUtc2NhbGVyIi4gIEN1cnJlbnRseSB3ZSBh cmUgbGlrZWx5IHRvIGVuZCB1cCB3aXRoIGFuCm9kZCBtdWx0aXBsaWVyIGV2ZW4gdGhvdWdoIHRo ZXJlIGlzIGFuIGVxdWl2YWxlbnQgc2V0IG9mIHBhcmFtZXRlcnMgd2l0aAphbiBldmVuIG11bHRp cGxpZXIuCgpGb3IgZXhhbXBsZSwgdXNpbmcgdGhlIDMyNE1IeiBiaXQgcmF0ZSB3aXRoIGEgcmVm ZXJlbmNlIGNsb2NrIG9mIDI0TUh6CndlIGVuZCB1cCB3aXRoIE0gPSAyNywgTiA9IDIgd2hlcmVh cyB0aGUgZXhhbXBsZSBpbiB0aGUgUEhZIGRhdGFib29rCmdpdmVzIE0gPSA1NCwgTiA9IDQgZm9y IHRoaXMgYml0IHJhdGUgYW5kIHJlZmVyZW5jZSBjbG9jay4KCkJ5IHdhbGtpbmcgZG93biB0aHJv dWdoIHRoZSBhdmFpbGFibGUgbXVsdGlwbGllciBpbnN0ZWFkIG9mIHVwIHdlIGFyZQptb3JlIGxp a2VseSB0byBoaXQgYW4gZXZlbiBtdWx0aXBsaWVyLiAgV2l0aCB0aGUgYWJvdmUgZXhhbXBsZSB3 ZSBkbyBub3cKZ2V0IE0gPSA1NCwgTiA9IDQgYXMgZ2l2ZW4gYnkgdGhlIGRhdGFib29rLgoKV2hp bGUgZG9pbmcgdGhpcywgY2hhbmdlIHRoZSBsb29wIGxpbWl0cyB0byBlbmNvZGUgdGhlIGFjdHVh bCBsaW1pdHMgb24KdGhlIGRpdmlzb3IsIHdoaWNoIGFyZToKCgk0ME1IeiA+PSAocGxscmVmIC8g TikgPj0gNU1IegoKU2lnbmVkLW9mZi1ieTogSm9obiBLZWVwaW5nIDxqb2huQG1ldGFuYXRlLmNv bT4KLS0tClVuY2hhbmdlZCBpbiB2MwpVbmNoYW5nZWQgaW4gdjIKCiBkcml2ZXJzL2dwdS9kcm0v cm9ja2NoaXAvZHctbWlwaS1kc2kuYyB8IDIgKy0KIDEgZmlsZSBjaGFuZ2VkLCAxIGluc2VydGlv bigrKSwgMSBkZWxldGlvbigtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hp cC9kdy1taXBpLWRzaS5jIGIvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL2R3LW1pcGktZHNpLmMK aW5kZXggODVlZGY2ZGQyYmFjLi5kY2I2NmEyMWUxZjEgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1 L2RybS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hp cC9kdy1taXBpLWRzaS5jCkBAIC01MjIsNyArNTIyLDcgQEAgc3RhdGljIGludCBkd19taXBpX2Rz aV9nZXRfbGFuZV9icHMoc3RydWN0IGR3X21pcGlfZHNpICpkc2ksCiAJcGxscmVmID0gRElWX1JP VU5EX1VQKGNsa19nZXRfcmF0ZShkc2ktPnBsbHJlZl9jbGspLCBVU0VDX1BFUl9TRUMpOwogCXRt cCA9IHBsbHJlZjsKIAotCWZvciAoaSA9IDE7IGkgPCA2OyBpKyspIHsKKwlmb3IgKGkgPSBwbGxy ZWYgLyA1OyBpID4gKHBsbHJlZiAvIDQwKTsgaS0tKSB7CiAJCXByZSA9IHBsbHJlZiAvIGk7CiAJ CWlmICgodG1wID4gKHRhcmdldF9tYnBzICUgcHJlKSkgJiYgKHRhcmdldF9tYnBzIC8gcHJlIDwg NTEyKSkgewogCQkJdG1wID0gdGFyZ2V0X21icHMgJSBwcmU7Ci0tIAoyLjExLjAuMTk3LmdiNTU2 ZGU1LmRpcnR5CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f XwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcK aHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 From: john@metanate.com (John Keeping) Date: Sun, 29 Jan 2017 13:24:37 +0000 Subject: [PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL configuration In-Reply-To: <20170129132444.25251-1-john@metanate.com> References: <20170129132444.25251-1-john@metanate.com> Message-ID: <20170129132444.25251-18-john@metanate.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org The multiplication ratio for the PLL is required to be even due to the use of a "by 2 pre-scaler". Currently we are likely to end up with an odd multiplier even though there is an equivalent set of parameters with an even multiplier. For example, using the 324MHz bit rate with a reference clock of 24MHz we end up with M = 27, N = 2 whereas the example in the PHY databook gives M = 54, N = 4 for this bit rate and reference clock. By walking down through the available multiplier instead of up we are more likely to hit an even multiplier. With the above example we do now get M = 54, N = 4 as given by the databook. While doing this, change the loop limits to encode the actual limits on the divisor, which are: 40MHz >= (pllref / N) >= 5MHz Signed-off-by: John Keeping --- Unchanged in v3 Unchanged in v2 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index 85edf6dd2bac..dcb66a21e1f1 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -522,7 +522,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi, pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC); tmp = pllref; - for (i = 1; i < 6; i++) { + for (i = pllref / 5; i > (pllref / 40); i--) { pre = pllref / i; if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) { tmp = target_mbps % pre; -- 2.11.0.197.gb556de5.dirty From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751617AbdA2PSy (ORCPT ); Sun, 29 Jan 2017 10:18:54 -0500 Received: from dougal.metanate.com ([90.155.101.14]:45028 "EHLO metanate.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751314AbdA2PR2 (ORCPT ); Sun, 29 Jan 2017 10:17:28 -0500 From: John Keeping To: Mark Yao Cc: Chris Zhong , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, John Keeping Subject: [PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL configuration Date: Sun, 29 Jan 2017 13:24:37 +0000 Message-Id: <20170129132444.25251-18-john@metanate.com> X-Mailer: git-send-email 2.11.0.197.gb556de5.dirty In-Reply-To: <20170129132444.25251-1-john@metanate.com> References: <20170129132444.25251-1-john@metanate.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The multiplication ratio for the PLL is required to be even due to the use of a "by 2 pre-scaler". Currently we are likely to end up with an odd multiplier even though there is an equivalent set of parameters with an even multiplier. For example, using the 324MHz bit rate with a reference clock of 24MHz we end up with M = 27, N = 2 whereas the example in the PHY databook gives M = 54, N = 4 for this bit rate and reference clock. By walking down through the available multiplier instead of up we are more likely to hit an even multiplier. With the above example we do now get M = 54, N = 4 as given by the databook. While doing this, change the loop limits to encode the actual limits on the divisor, which are: 40MHz >= (pllref / N) >= 5MHz Signed-off-by: John Keeping --- Unchanged in v3 Unchanged in v2 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index 85edf6dd2bac..dcb66a21e1f1 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -522,7 +522,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi, pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC); tmp = pllref; - for (i = 1; i < 6; i++) { + for (i = pllref / 5; i > (pllref / 40); i--) { pre = pllref / i; if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) { tmp = target_mbps % pre; -- 2.11.0.197.gb556de5.dirty