From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sean Paul Subject: Re: [PATCH v3 09/24] drm/rockchip: dw-mipi-dsi: only request HS clock when required Date: Mon, 30 Jan 2017 13:20:30 -0500 Message-ID: <20170130182030.GJ20076@art_vandelay> References: <20170129132444.25251-1-john@metanate.com> <20170129132444.25251-10-john@metanate.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <20170129132444.25251-10-john@metanate.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: John Keeping Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Chris Zhong , linux-arm-kernel@lists.infradead.org List-Id: linux-rockchip.vger.kernel.org T24gU3VuLCBKYW4gMjksIDIwMTcgYXQgMDE6MjQ6MjlQTSArMDAwMCwgSm9obiBLZWVwaW5nIHdy b3RlOgo+IFJlcXVlc3RpbmcgdGhlIEhTIGNsb2NrIGZyb20gdGhlIFBIWSBiZWZvcmUgd2UgaW5p dGlhbGl6ZSBpdCBjYXVzZXMgYW4KPiBpbnZhbGlkIHNpZ25hbCB0byBiZSBzZW50IG91dCBzaW5j ZSB0aGUgaW5wdXQgY2xvY2sgaXMgbm90IHlldAo+IGNvbmZpZ3VyZWQuICBUaGUgUEhZIGRhdGFi b29rIHN1Z2dlc3RzIG9ubHkgYXNzZXJ0aW5nIHRoaXMgc2lnbmFsIHdoZW4KPiBwZXJmb3JtaW5n IEhTIHRyYW5zZmVycywgc28gbGV0J3MgZG8gdGhhdC4KPiAKClJldmlld2VkLWJ5OiBTZWFuIFBh dWwgPHNlYW5wYXVsQGNocm9taXVtLm9yZz4KCj4gU2lnbmVkLW9mZi1ieTogSm9obiBLZWVwaW5n IDxqb2huQG1ldGFuYXRlLmNvbT4KPiBSZXZpZXdlZC1ieTogQ2hyaXMgWmhvbmcgPHp5d0Byb2Nr LWNoaXBzLmNvbT4KPiAtLS0KPiB2MzoKPiAtIEFkZCBDaHJpcycgUmV2aWV3ZWQtYnkKPiBVbmNo YW5nZWQgaW4gdjIKPiAKPiAgZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL2R3LW1pcGktZHNpLmMg fCA2ICsrKystLQo+ICAxIGZpbGUgY2hhbmdlZCwgNCBpbnNlcnRpb25zKCspLCAyIGRlbGV0aW9u cygtKQo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvZHctbWlwaS1k c2kuYyBiL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jCj4gaW5kZXggMTVk MzNjM2M4Y2I3Li4wM2ZjMDk2ZmUxYmQgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL3Jv Y2tjaGlwL2R3LW1pcGktZHNpLmMKPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvZHct bWlwaS1kc2kuYwo+IEBAIC01NDUsMTMgKzU0NSwxNSBAQCBzdGF0aWMgaW50IGR3X21pcGlfZHNp X2hvc3RfZGV0YWNoKHN0cnVjdCBtaXBpX2RzaV9ob3N0ICpob3N0LAo+ICBzdGF0aWMgdm9pZCBk d19taXBpX21lc3NhZ2VfY29uZmlnKHN0cnVjdCBkd19taXBpX2RzaSAqZHNpLAo+ICAJCQkJICAg Y29uc3Qgc3RydWN0IG1pcGlfZHNpX21zZyAqbXNnKQo+ICB7Cj4gKwlib29sIGxwbSA9IG1zZy0+ ZmxhZ3MgJiBNSVBJX0RTSV9NU0dfVVNFX0xQTTsKPiAgCXUzMiB2YWwgPSAwOwo+ICAKPiAgCWlm IChtc2ctPmZsYWdzICYgTUlQSV9EU0lfTVNHX1JFUV9BQ0spCj4gIAkJdmFsIHw9IEVOX0FDS19S UVNUOwo+IC0JaWYgKG1zZy0+ZmxhZ3MgJiBNSVBJX0RTSV9NU0dfVVNFX0xQTSkKPiArCWlmIChs cG0pCj4gIAkJdmFsIHw9IENNRF9NT0RFX0FMTF9MUDsKPiAgCj4gKwlkc2lfd3JpdGUoZHNpLCBE U0lfTFBDTEtfQ1RSTCwgbHBtID8gMCA6IFBIWV9UWFJFUVVFU1RDTEtIUyk7Cj4gIAlkc2lfd3Jp dGUoZHNpLCBEU0lfQ01EX01PREVfQ0ZHLCB2YWwpOwo+ICB9Cj4gIAo+IEBAIC02OTMsNiArNjk1 LDcgQEAgc3RhdGljIHZvaWQgZHdfbWlwaV9kc2lfc2V0X21vZGUoc3RydWN0IGR3X21pcGlfZHNp ICpkc2ksCj4gIAkJZHNpX3dyaXRlKGRzaSwgRFNJX1BXUl9VUCwgUkVTRVQpOwo+ICAJCWRzaV93 cml0ZShkc2ksIERTSV9NT0RFX0NGRywgRU5BQkxFX1ZJREVPX01PREUpOwo+ICAJCWR3X21pcGlf ZHNpX3ZpZGVvX21vZGVfY29uZmlnKGRzaSk7Cj4gKwkJZHNpX3dyaXRlKGRzaSwgRFNJX0xQQ0xL X0NUUkwsIFBIWV9UWFJFUVVFU1RDTEtIUyk7Cj4gIAkJZHNpX3dyaXRlKGRzaSwgRFNJX1BXUl9V UCwgUE9XRVJVUCk7Cj4gIAl9Cj4gIH0KPiBAQCAtNzEwLDcgKzcxMyw2IEBAIHN0YXRpYyB2b2lk IGR3X21pcGlfZHNpX2luaXQoc3RydWN0IGR3X21pcGlfZHNpICpkc2kpCj4gIAkJICB8IFBIWV9S U1RaIHwgUEhZX1NIVVRET1dOWik7Cj4gIAlkc2lfd3JpdGUoZHNpLCBEU0lfQ0xLTUdSX0NGRywg VE9fQ0xLX0RJVklEU0lPTigxMCkgfAo+ICAJCSAgVFhfRVNDX0NMS19ESVZJRFNJT04oNykpOwo+ IC0JZHNpX3dyaXRlKGRzaSwgRFNJX0xQQ0xLX0NUUkwsIFBIWV9UWFJFUVVFU1RDTEtIUyk7Cj4g IH0KPiAgCj4gIHN0YXRpYyB2b2lkIGR3X21pcGlfZHNpX2RwaV9jb25maWcoc3RydWN0IGR3X21p cGlfZHNpICpkc2ksCj4gLS0gCj4gMi4xMS4wLjE5Ny5nYjU1NmRlNS5kaXJ0eQo+IAo+IF9fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCj4gZHJpLWRldmVsIG1h aWxpbmcgbGlzdAo+IGRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKPiBodHRwczovL2xp c3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAoKLS0gClNlYW4g UGF1bCwgU29mdHdhcmUgRW5naW5lZXIsIEdvb2dsZSAvIENocm9taXVtIE9TCl9fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxp c3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNr dG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: seanpaul@chromium.org (Sean Paul) Date: Mon, 30 Jan 2017 13:20:30 -0500 Subject: [PATCH v3 09/24] drm/rockchip: dw-mipi-dsi: only request HS clock when required In-Reply-To: <20170129132444.25251-10-john@metanate.com> References: <20170129132444.25251-1-john@metanate.com> <20170129132444.25251-10-john@metanate.com> Message-ID: <20170130182030.GJ20076@art_vandelay> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Sun, Jan 29, 2017 at 01:24:29PM +0000, John Keeping wrote: > Requesting the HS clock from the PHY before we initialize it causes an > invalid signal to be sent out since the input clock is not yet > configured. The PHY databook suggests only asserting this signal when > performing HS transfers, so let's do that. > Reviewed-by: Sean Paul > Signed-off-by: John Keeping > Reviewed-by: Chris Zhong > --- > v3: > - Add Chris' Reviewed-by > Unchanged in v2 > > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index 15d33c3c8cb7..03fc096fe1bd 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -545,13 +545,15 @@ static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, > static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, > const struct mipi_dsi_msg *msg) > { > + bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM; > u32 val = 0; > > if (msg->flags & MIPI_DSI_MSG_REQ_ACK) > val |= EN_ACK_RQST; > - if (msg->flags & MIPI_DSI_MSG_USE_LPM) > + if (lpm) > val |= CMD_MODE_ALL_LP; > > + dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS); > dsi_write(dsi, DSI_CMD_MODE_CFG, val); > } > > @@ -693,6 +695,7 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, > dsi_write(dsi, DSI_PWR_UP, RESET); > dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); > dw_mipi_dsi_video_mode_config(dsi); > + dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); > dsi_write(dsi, DSI_PWR_UP, POWERUP); > } > } > @@ -710,7 +713,6 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) > | PHY_RSTZ | PHY_SHUTDOWNZ); > dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | > TX_ESC_CLK_DIVIDSION(7)); > - dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); > } > > static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, > -- > 2.11.0.197.gb556de5.dirty > > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Sean Paul, Software Engineer, Google / Chromium OS From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754073AbdA3SUe (ORCPT ); Mon, 30 Jan 2017 13:20:34 -0500 Received: from mail-qt0-f172.google.com ([209.85.216.172]:34753 "EHLO mail-qt0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753600AbdA3SUd (ORCPT ); Mon, 30 Jan 2017 13:20:33 -0500 Date: Mon, 30 Jan 2017 13:20:30 -0500 From: Sean Paul To: John Keeping Cc: Mark Yao , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Chris Zhong , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 09/24] drm/rockchip: dw-mipi-dsi: only request HS clock when required Message-ID: <20170130182030.GJ20076@art_vandelay> References: <20170129132444.25251-1-john@metanate.com> <20170129132444.25251-10-john@metanate.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170129132444.25251-10-john@metanate.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Jan 29, 2017 at 01:24:29PM +0000, John Keeping wrote: > Requesting the HS clock from the PHY before we initialize it causes an > invalid signal to be sent out since the input clock is not yet > configured. The PHY databook suggests only asserting this signal when > performing HS transfers, so let's do that. > Reviewed-by: Sean Paul > Signed-off-by: John Keeping > Reviewed-by: Chris Zhong > --- > v3: > - Add Chris' Reviewed-by > Unchanged in v2 > > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index 15d33c3c8cb7..03fc096fe1bd 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -545,13 +545,15 @@ static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, > static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, > const struct mipi_dsi_msg *msg) > { > + bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM; > u32 val = 0; > > if (msg->flags & MIPI_DSI_MSG_REQ_ACK) > val |= EN_ACK_RQST; > - if (msg->flags & MIPI_DSI_MSG_USE_LPM) > + if (lpm) > val |= CMD_MODE_ALL_LP; > > + dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS); > dsi_write(dsi, DSI_CMD_MODE_CFG, val); > } > > @@ -693,6 +695,7 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, > dsi_write(dsi, DSI_PWR_UP, RESET); > dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); > dw_mipi_dsi_video_mode_config(dsi); > + dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); > dsi_write(dsi, DSI_PWR_UP, POWERUP); > } > } > @@ -710,7 +713,6 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) > | PHY_RSTZ | PHY_SHUTDOWNZ); > dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | > TX_ESC_CLK_DIVIDSION(7)); > - dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); > } > > static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, > -- > 2.11.0.197.gb556de5.dirty > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Sean Paul, Software Engineer, Google / Chromium OS