[U-Boot] [PATCH 0/1] Fix H-PLL and M-PLL clock rate calculation in ast2500 clock driver

[U-Boot] [PATCH 0/1] Fix H-PLL and M-PLL clock rate calculation in ast2500 clock driver

[Maxim Sloyko]

This is a fix to a very dumb (division by zero) mistake I made in the
series where I added support for ast2500 eval board. It is not causing
any problems for that board yet, because no driver requests the rate of
any clock yet, but I think it's still better to fix it for this release.


Maxim Sloyko (1):
  aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation

 drivers/clk/aspeed/clk_ast2500.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH 1/1] aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation

[Maxim Sloyko]

Fix H-PLL and M-PLL rate calculation in ast2500 clock driver.
Without this fix, valid setting can lead to division by zero
when requesting the rate of H-PLL or M-PLL clocks.

Signed-off-by: Maxim Sloyko <maxims@google.com>

---

---
 drivers/clk/aspeed/clk_ast2500.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index af369cc4c8..26a5e58221 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -35,7 +35,7 @@ static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
 	const ulong post_div = (mpll_reg >> SCU_MPLL_POST_SHIFT)
 			& SCU_MPLL_POST_MASK;
 
-	return (clkin * ((num + 1) / (denum + 1))) / post_div;
+	return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
 }
 
 /*
@@ -50,7 +50,7 @@ static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
 	const ulong post_div = (hpll_reg >> SCU_HPLL_POST_SHIFT)
 			& SCU_HPLL_POST_MASK;
 
-	return (clkin * ((num + 1) / (denum + 1))) / post_div;
+	return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
 }
 
 static ulong ast2500_get_clkin(struct ast2500_scu *scu)
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH 1/1] aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation

[Simon Glass]

On 30 January 2017 at 12:35, Maxim Sloyko <maxims@google.com> wrote:
>
> Fix H-PLL and M-PLL rate calculation in ast2500 clock driver.
> Without this fix, valid setting can lead to division by zero
> when requesting the rate of H-PLL or M-PLL clocks.
>
> Signed-off-by: Maxim Sloyko <maxims@google.com>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [U-Boot, 1/1] aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation

[Tom Rini]

On Mon, Jan 30, 2017 at 11:35:04AM -0800, maxims at google.com wrote:

> Fix H-PLL and M-PLL rate calculation in ast2500 clock driver.
> Without this fix, valid setting can lead to division by zero
> when requesting the rate of H-PLL or M-PLL clocks.
> 
> Signed-off-by: Maxim Sloyko <maxims@google.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>

Applied to u-boot/master, thanks!

-- 
Tom
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