From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxim Sloyko Date: Mon, 30 Jan 2017 11:35:04 -0800 Subject: [U-Boot] [PATCH 1/1] aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation In-Reply-To: <20170130193504.11325-1-maxims@google.com> References: <20170130193504.11325-1-maxims@google.com> Message-ID: <20170130193504.11325-2-maxims@google.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Fix H-PLL and M-PLL rate calculation in ast2500 clock driver. Without this fix, valid setting can lead to division by zero when requesting the rate of H-PLL or M-PLL clocks. Signed-off-by: Maxim Sloyko --- --- drivers/clk/aspeed/clk_ast2500.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index af369cc4c8..26a5e58221 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -35,7 +35,7 @@ static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg) const ulong post_div = (mpll_reg >> SCU_MPLL_POST_SHIFT) & SCU_MPLL_POST_MASK; - return (clkin * ((num + 1) / (denum + 1))) / post_div; + return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); } /* @@ -50,7 +50,7 @@ static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg) const ulong post_div = (hpll_reg >> SCU_HPLL_POST_SHIFT) & SCU_HPLL_POST_MASK; - return (clkin * ((num + 1) / (denum + 1))) / post_div; + return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); } static ulong ast2500_get_clkin(struct ast2500_scu *scu) -- 2.11.0.483.g087da7b7c-goog