From mboxrd@z Thu Jan 1 00:00:00 1970 From: John Keeping Subject: Re: [PATCH v3 16/24] drm/rockchip: dw-mipi-dsi: properly configure PHY timing Date: Tue, 31 Jan 2017 12:39:17 +0000 Message-ID: <20170131123917.6347ab94.john@metanate.com> References: <20170129132444.25251-1-john@metanate.com> <20170129132444.25251-17-john@metanate.com> <20170130215736.GT20076@art_vandelay> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20170130215736.GT20076@art_vandelay> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Sean Paul Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Chris Zhong , linux-arm-kernel@lists.infradead.org List-Id: linux-rockchip.vger.kernel.org T24gTW9uLCAzMCBKYW4gMjAxNyAxNjo1NzozNiAtMDUwMCwgU2VhbiBQYXVsIHdyb3RlOgoKPiBP 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X19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9w Lm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1k ZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: john@metanate.com (John Keeping) Date: Tue, 31 Jan 2017 12:39:17 +0000 Subject: [PATCH v3 16/24] drm/rockchip: dw-mipi-dsi: properly configure PHY timing In-Reply-To: <20170130215736.GT20076@art_vandelay> References: <20170129132444.25251-1-john@metanate.com> <20170129132444.25251-17-john@metanate.com> <20170130215736.GT20076@art_vandelay> Message-ID: <20170131123917.6347ab94.john@metanate.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, 30 Jan 2017 16:57:36 -0500, Sean Paul wrote: > On Sun, Jan 29, 2017 at 01:24:36PM +0000, John Keeping wrote: > > These values are specified as constant time periods but the PHY > > configuration is in terms of the current lane byte clock so using > > constant values guarantees that the timings will be outside the > > specification with some display configurations. > > > > Derive the necessary configuration from the byte clock in order to > > ensure that the PHY configuration is correct. > > > > Signed-off-by: John Keeping > > --- > > v3: > > - Wrap some long lines > > Unchanged in v2 > > > > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 39 ++++++++++++++++++++++++++++++---- > > 1 file changed, 35 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > > index cfe7e4ba305c..85edf6dd2bac 100644 > > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > > @@ -383,6 +383,26 @@ static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code, > > dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); > > } > > > > +/** > > + * ns2bc - Nanoseconds to byte clock cycles > > + */ > > +static inline unsigned int ns2bc(struct dw_mipi_dsi *dsi, int ns) > > +{ > > + unsigned long byte_clk_khz = dsi->lane_mbps * MSEC_PER_SEC / 8; > > Why multiply by 1000 (MSEC_PER_SEC) only to immediately divide by 1000? > > > + > > + return (ns * (byte_clk_khz / 1000) + 999) / 1000; > > Can you replace this whole function with: > > return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); Yes, I'll make this simplification. > > +} > > + > > +/** > > + * ns2ui - Nanoseconds to UI time periods > > + */ > > +static inline unsigned int ns2ui(struct dw_mipi_dsi *dsi, int ns) > > +{ > > + unsigned long byte_clk_khz = dsi->lane_mbps * MSEC_PER_SEC; > > + > > + return (ns * (byte_clk_khz / 1000) + 999) / 1000; > > Same remarks here. > > Sean > > > > +} > > + > > static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > > { > > int ret, testdin, vco, val; > > @@ -434,10 +454,21 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > > SETRD_MAX | POWER_MANAGE | > > TER_RESISTORS_ON); > > > > - > > - dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf); > > - dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55); > > - dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa); > > + dw_mipi_dsi_phy_write(dsi, 0x60, TLP_PROGRAM_EN | ns2bc(dsi, 500)); > > + dw_mipi_dsi_phy_write(dsi, 0x61, THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); > > + dw_mipi_dsi_phy_write(dsi, 0x62, THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); > > + dw_mipi_dsi_phy_write(dsi, 0x63, THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); > > + dw_mipi_dsi_phy_write(dsi, 0x64, BIT(5) | ns2bc(dsi, 100)); > > + dw_mipi_dsi_phy_write(dsi, 0x65, BIT(5) | (ns2bc(dsi, 60) + 7)); > > + > > + dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | ns2bc(dsi, 500)); > > + dw_mipi_dsi_phy_write(dsi, 0x71, > > + THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 5)); > > + dw_mipi_dsi_phy_write(dsi, 0x72, > > + THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); > > + dw_mipi_dsi_phy_write(dsi, 0x73, > > + THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); > > + dw_mipi_dsi_phy_write(dsi, 0x74, BIT(5) | ns2bc(dsi, 100)); > > > > dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | > > PHY_UNRSTZ | PHY_UNSHUTDOWNZ); > > -- > > 2.11.0.197.gb556de5.dirty > > > > _______________________________________________ > > dri-devel mailing list > > dri-devel at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/dri-devel > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752077AbdAaMje (ORCPT ); Tue, 31 Jan 2017 07:39:34 -0500 Received: from dougal.metanate.com ([90.155.101.14]:64770 "EHLO metanate.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751726AbdAaMjX (ORCPT ); Tue, 31 Jan 2017 07:39:23 -0500 Date: Tue, 31 Jan 2017 12:39:17 +0000 From: John Keeping To: Sean Paul Cc: Mark Yao , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Chris Zhong , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 16/24] drm/rockchip: dw-mipi-dsi: properly configure PHY timing Message-ID: <20170131123917.6347ab94.john@metanate.com> In-Reply-To: <20170130215736.GT20076@art_vandelay> References: <20170129132444.25251-1-john@metanate.com> <20170129132444.25251-17-john@metanate.com> <20170130215736.GT20076@art_vandelay> Organization: Metanate Ltd X-Mailer: Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 30 Jan 2017 16:57:36 -0500, Sean Paul wrote: > On Sun, Jan 29, 2017 at 01:24:36PM +0000, John Keeping wrote: > > These values are specified as constant time periods but the PHY > > configuration is in terms of the current lane byte clock so using > > constant values guarantees that the timings will be outside the > > specification with some display configurations. > > > > Derive the necessary configuration from the byte clock in order to > > ensure that the PHY configuration is correct. > > > > Signed-off-by: John Keeping > > --- > > v3: > > - Wrap some long lines > > Unchanged in v2 > > > > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 39 ++++++++++++++++++++++++++++++---- > > 1 file changed, 35 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > > index cfe7e4ba305c..85edf6dd2bac 100644 > > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > > @@ -383,6 +383,26 @@ static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code, > > dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); > > } > > > > +/** > > + * ns2bc - Nanoseconds to byte clock cycles > > + */ > > +static inline unsigned int ns2bc(struct dw_mipi_dsi *dsi, int ns) > > +{ > > + unsigned long byte_clk_khz = dsi->lane_mbps * MSEC_PER_SEC / 8; > > Why multiply by 1000 (MSEC_PER_SEC) only to immediately divide by 1000? > > > + > > + return (ns * (byte_clk_khz / 1000) + 999) / 1000; > > Can you replace this whole function with: > > return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); Yes, I'll make this simplification. > > +} > > + > > +/** > > + * ns2ui - Nanoseconds to UI time periods > > + */ > > +static inline unsigned int ns2ui(struct dw_mipi_dsi *dsi, int ns) > > +{ > > + unsigned long byte_clk_khz = dsi->lane_mbps * MSEC_PER_SEC; > > + > > + return (ns * (byte_clk_khz / 1000) + 999) / 1000; > > Same remarks here. > > Sean > > > > +} > > + > > static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > > { > > int ret, testdin, vco, val; > > @@ -434,10 +454,21 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > > SETRD_MAX | POWER_MANAGE | > > TER_RESISTORS_ON); > > > > - > > - dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf); > > - dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55); > > - dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa); > > + dw_mipi_dsi_phy_write(dsi, 0x60, TLP_PROGRAM_EN | ns2bc(dsi, 500)); > > + dw_mipi_dsi_phy_write(dsi, 0x61, THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); > > + dw_mipi_dsi_phy_write(dsi, 0x62, THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); > > + dw_mipi_dsi_phy_write(dsi, 0x63, THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); > > + dw_mipi_dsi_phy_write(dsi, 0x64, BIT(5) | ns2bc(dsi, 100)); > > + dw_mipi_dsi_phy_write(dsi, 0x65, BIT(5) | (ns2bc(dsi, 60) + 7)); > > + > > + dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | ns2bc(dsi, 500)); > > + dw_mipi_dsi_phy_write(dsi, 0x71, > > + THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 5)); > > + dw_mipi_dsi_phy_write(dsi, 0x72, > > + THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); > > + dw_mipi_dsi_phy_write(dsi, 0x73, > > + THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); > > + dw_mipi_dsi_phy_write(dsi, 0x74, BIT(5) | ns2bc(dsi, 100)); > > > > dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | > > PHY_UNRSTZ | PHY_UNSHUTDOWNZ); > > -- > > 2.11.0.197.gb556de5.dirty > > > > _______________________________________________ > > dri-devel mailing list > > dri-devel@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/dri-devel >