From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sean Paul Subject: Re: [PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL configuration Date: Tue, 31 Jan 2017 14:03:52 -0500 Message-ID: <20170131190352.GB20076@art_vandelay> References: <20170129132444.25251-1-john@metanate.com> <20170129132444.25251-18-john@metanate.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <20170129132444.25251-18-john@metanate.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: John Keeping Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Chris Zhong , linux-arm-kernel@lists.infradead.org List-Id: linux-rockchip.vger.kernel.org T24gU3VuLCBKYW4gMjksIDIwMTcgYXQgMDE6MjQ6MzdQTSArMDAwMCwgSm9obiBLZWVwaW5nIHdy b3RlOgo+IFRoZSBtdWx0aXBsaWNhdGlvbiByYXRpbyBmb3IgdGhlIFBMTCBpcyByZXF1aXJlZCB0 byBiZSBldmVuIGR1ZSB0byB0aGUKPiB1c2Ugb2YgYSAiYnkgMiBwcmUtc2NhbGVyIi4gIEN1cnJl bnRseSB3ZSBhcmUgbGlrZWx5IHRvIGVuZCB1cCB3aXRoIGFuCj4gb2RkIG11bHRpcGxpZXIgZXZl biB0aG91Z2ggdGhlcmUgaXMgYW4gZXF1aXZhbGVudCBzZXQgb2YgcGFyYW1ldGVycyB3aXRoCj4g YW4gZXZlbiBtdWx0aXBsaWVyLgo+IAo+IEZvciBleGFtcGxlLCB1c2luZyB0aGUgMzI0TUh6IGJp dCByYXRlIHdpdGggYSByZWZlcmVuY2UgY2xvY2sgb2YgMjRNSHoKPiB3ZSBlbmQgdXAgd2l0aCBN ID0gMjcsIE4gPSAyIHdoZXJlYXMgdGhlIGV4YW1wbGUgaW4gdGhlIFBIWSBkYXRhYm9vawo+IGdp dmVzIE0gPSA1NCwgTiA9IDQgZm9yIHRoaXMgYml0IHJhdGUgYW5kIHJlZmVyZW5jZSBjbG9jay4K PiAKPiBCeSB3YWxraW5nIGRvd24gdGhyb3VnaCB0aGUgYXZhaWxhYmxlIG11bHRpcGxpZXIgaW5z dGVhZCBvZiB1cCB3ZSBhcmUKPiBtb3JlIGxpa2VseSB0byBoaXQgYW4gZXZlbiBtdWx0aXBsaWVy LiAgV2l0aCB0aGUgYWJvdmUgZXhhbXBsZSB3ZSBkbyBub3cKPiBnZXQgTSA9IDU0LCBOID0gNCBh cyBnaXZlbiBieSB0aGUgZGF0YWJvb2suCj4gCj4gV2hpbGUgZG9pbmcgdGhpcywgY2hhbmdlIHRo ZSBsb29wIGxpbWl0cyB0byBlbmNvZGUgdGhlIGFjdHVhbCBsaW1pdHMgb24KPiB0aGUgZGl2aXNv ciwgd2hpY2ggYXJlOgo+IAo+IAk0ME1IeiA+PSAocGxscmVmIC8gTikgPj0gNU1Iego+IAo+IFNp Z25lZC1vZmYtYnk6IEpvaG4gS2VlcGluZyA8am9obkBtZXRhbmF0ZS5jb20+Cj4gLS0tCj4gVW5j aGFuZ2VkIGluIHYzCj4gVW5jaGFuZ2VkIGluIHYyCj4gCj4gIGRyaXZlcnMvZ3B1L2RybS9yb2Nr Y2hpcC9kdy1taXBpLWRzaS5jIHwgMiArLQo+ICAxIGZpbGUgY2hhbmdlZCwgMSBpbnNlcnRpb24o KyksIDEgZGVsZXRpb24oLSkKPiAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL3JvY2tj aGlwL2R3LW1pcGktZHNpLmMgYi9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvZHctbWlwaS1kc2ku Ywo+IGluZGV4IDg1ZWRmNmRkMmJhYy4uZGNiNjZhMjFlMWYxIDEwMDY0NAo+IC0tLSBhL2RyaXZl cnMvZ3B1L2RybS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJt L3JvY2tjaGlwL2R3LW1pcGktZHNpLmMKPiBAQCAtNTIyLDcgKzUyMiw3IEBAIHN0YXRpYyBpbnQg ZHdfbWlwaV9kc2lfZ2V0X2xhbmVfYnBzKHN0cnVjdCBkd19taXBpX2RzaSAqZHNpLAo+ICAJcGxs cmVmID0gRElWX1JPVU5EX1VQKGNsa19nZXRfcmF0ZShkc2ktPnBsbHJlZl9jbGspLCBVU0VDX1BF Ul9TRUMpOwo+ICAJdG1wID0gcGxscmVmOwo+ICAKPiAtCWZvciAoaSA9IDE7IGkgPCA2OyBpKysp IHsKPiArCWZvciAoaSA9IHBsbHJlZiAvIDU7IGkgPiAocGxscmVmIC8gNDApOyBpLS0pIHsKCkkn dmUgY29udmluY2VkIG15c2VsZiB0aGF0IHRoaXMgaXMgcmlnaHQsIGJ1dCBpdCB0b29rIHJlYWRp bmcgdGhyb3VnaCB0aGUgY29tbWl0Cm1lc3NhZ2UgYSBmZXcgdGltZXMuIEkgdGhpbmsgdGhpcyBj b2RlIHdvdWxkIGJlbmVmaXQgZ3JlYXRseSBmcm9tIGEgY29tbWVudCBzbwpyZWFkZXJzIGRvbid0 IG5lZWQgdG8gZ28gdGhyb3VnaCBnaXQgaGlzdG9yeS4KCldpdGggdGhhdCwKClJldmlld2VkLWJ5 OiBTZWFuIFBhdWwgPHNlYW5wYXVsQGNocm9taXVtLm9yZz4KCgo+ICAJCXByZSA9IHBsbHJlZiAv IGk7Cj4gIAkJaWYgKCh0bXAgPiAodGFyZ2V0X21icHMgJSBwcmUpKSAmJiAodGFyZ2V0X21icHMg LyBwcmUgPCA1MTIpKSB7Cj4gIAkJCXRtcCA9IHRhcmdldF9tYnBzICUgcHJlOwo+IC0tIAo+IDIu MTEuMC4xOTcuZ2I1NTZkZTUuZGlydHkKPiAKPiBfX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fXwo+IGRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKPiBkcmktZGV2ZWxA bGlzdHMuZnJlZWRlc2t0b3Aub3JnCj4gaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFp bG1hbi9saXN0aW5mby9kcmktZGV2ZWwKCi0tIApTZWFuIFBhdWwsIFNvZnR3YXJlIEVuZ2luZWVy LCBHb29nbGUgLyBDaHJvbWl1bSBPUwpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVl ZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5m by9kcmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 From: seanpaul@chromium.org (Sean Paul) Date: Tue, 31 Jan 2017 14:03:52 -0500 Subject: [PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL configuration In-Reply-To: <20170129132444.25251-18-john@metanate.com> References: <20170129132444.25251-1-john@metanate.com> <20170129132444.25251-18-john@metanate.com> Message-ID: <20170131190352.GB20076@art_vandelay> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Sun, Jan 29, 2017 at 01:24:37PM +0000, John Keeping wrote: > The multiplication ratio for the PLL is required to be even due to the > use of a "by 2 pre-scaler". Currently we are likely to end up with an > odd multiplier even though there is an equivalent set of parameters with > an even multiplier. > > For example, using the 324MHz bit rate with a reference clock of 24MHz > we end up with M = 27, N = 2 whereas the example in the PHY databook > gives M = 54, N = 4 for this bit rate and reference clock. > > By walking down through the available multiplier instead of up we are > more likely to hit an even multiplier. With the above example we do now > get M = 54, N = 4 as given by the databook. > > While doing this, change the loop limits to encode the actual limits on > the divisor, which are: > > 40MHz >= (pllref / N) >= 5MHz > > Signed-off-by: John Keeping > --- > Unchanged in v3 > Unchanged in v2 > > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index 85edf6dd2bac..dcb66a21e1f1 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -522,7 +522,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi, > pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC); > tmp = pllref; > > - for (i = 1; i < 6; i++) { > + for (i = pllref / 5; i > (pllref / 40); i--) { I've convinced myself that this is right, but it took reading through the commit message a few times. I think this code would benefit greatly from a comment so readers don't need to go through git history. With that, Reviewed-by: Sean Paul > pre = pllref / i; > if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) { > tmp = target_mbps % pre; > -- > 2.11.0.197.gb556de5.dirty > > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Sean Paul, Software Engineer, Google / Chromium OS From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751848AbdAaTKh (ORCPT ); Tue, 31 Jan 2017 14:10:37 -0500 Received: from mail-qk0-f173.google.com ([209.85.220.173]:34658 "EHLO mail-qk0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751515AbdAaTKf (ORCPT ); Tue, 31 Jan 2017 14:10:35 -0500 Date: Tue, 31 Jan 2017 14:03:52 -0500 From: Sean Paul To: John Keeping Cc: Mark Yao , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Chris Zhong , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL configuration Message-ID: <20170131190352.GB20076@art_vandelay> References: <20170129132444.25251-1-john@metanate.com> <20170129132444.25251-18-john@metanate.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170129132444.25251-18-john@metanate.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Jan 29, 2017 at 01:24:37PM +0000, John Keeping wrote: > The multiplication ratio for the PLL is required to be even due to the > use of a "by 2 pre-scaler". Currently we are likely to end up with an > odd multiplier even though there is an equivalent set of parameters with > an even multiplier. > > For example, using the 324MHz bit rate with a reference clock of 24MHz > we end up with M = 27, N = 2 whereas the example in the PHY databook > gives M = 54, N = 4 for this bit rate and reference clock. > > By walking down through the available multiplier instead of up we are > more likely to hit an even multiplier. With the above example we do now > get M = 54, N = 4 as given by the databook. > > While doing this, change the loop limits to encode the actual limits on > the divisor, which are: > > 40MHz >= (pllref / N) >= 5MHz > > Signed-off-by: John Keeping > --- > Unchanged in v3 > Unchanged in v2 > > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index 85edf6dd2bac..dcb66a21e1f1 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -522,7 +522,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi, > pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC); > tmp = pllref; > > - for (i = 1; i < 6; i++) { > + for (i = pllref / 5; i > (pllref / 40); i--) { I've convinced myself that this is right, but it took reading through the commit message a few times. I think this code would benefit greatly from a comment so readers don't need to go through git history. With that, Reviewed-by: Sean Paul > pre = pllref / i; > if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) { > tmp = target_mbps % pre; > -- > 2.11.0.197.gb556de5.dirty > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Sean Paul, Software Engineer, Google / Chromium OS