From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sean Paul Subject: Re: [PATCH v3 23/24] drm/rockchip: dw-mipi-dsi: add reset control Date: Tue, 31 Jan 2017 14:28:07 -0500 Message-ID: <20170131192807.GG20076@art_vandelay> References: <20170129132444.25251-1-john@metanate.com> <20170129132444.25251-24-john@metanate.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <20170129132444.25251-24-john@metanate.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: John Keeping Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Chris Zhong , linux-arm-kernel@lists.infradead.org List-Id: linux-rockchip.vger.kernel.org T24gU3VuLCBKYW4gMjksIDIwMTcgYXQgMDE6MjQ6NDNQTSArMDAwMCwgSm9obiBLZWVwaW5nIHdy b3RlOgo+IEluIG9yZGVyIHRvIGZ1bGx5IHJlc2V0IHRoZSBzdGF0ZSBvZiB0aGUgTUlQSSBjb250 cm9sbGVyIHdlIG11c3QgYXNzZXJ0Cj4gdGhpcyByZXNldC4KPiAKPiBUaGlzIGlzIHNsaWdodGx5 IG1vcmUgY29tcGxpY2F0ZWQgdGhhbiBpdCBjb3VsZCBiZSBpbiBvcmRlciB0byBtYWludGFpbgo+ IGNvbXBhdGliaWxpdHkgd2l0aCBkZXZpY2UgdHJlZXMgdGhhdCBkbyBub3Qgc3BlY2lmeSB0aGUg cmVzZXQgcHJvcGVydHkuCj4gCgpJIGFsd2F5cyBmaW5kIGl0IGEgbGl0dGxlIGdyYXRpbmcgdG8g c2VlIGEgZGV2aWNlIG1hbmFnZWQgcmVzb3VyY2UgZ2l2ZW4gdG8gYQpsb2NhbCB2YXJpYWJsZSB0 aGF0IGlzIHVzZWQgaW1tZWRpYXRlbHkgYW5kIG9ubHkgb25jZS4gSG93ZXZlciwgSSB0aGluayB0 aGlzCm1pZ2h0IGp1c3QgYmUgb25lIG9mIG15IHR3aXRjaGVzLiBTbyBub3cgdGhhdCBJJ3ZlIGFp cmVkIG15IGdyaWV2YW5jZSwgCgpSZXZpZXdlZC1ieTogU2VhbiBQYXVsIDxzZWFucGF1bEBjaHJv bWl1bS5vcmc+Cgo+IFNpZ25lZC1vZmYtYnk6IEpvaG4gS2VlcGluZyA8am9obkBtZXRhbmF0ZS5j b20+Cj4gUmV2aWV3ZWQtYnk6IENocmlzIFpob25nIDx6eXdAcm9jay1jaGlwcy5jb20+Cj4gLS0t Cj4gdjM6Cj4gLSBBZGQgQ2hyaXMnIFJldmlld2VkLWJ5Cj4gVW5jaGFuZ2VkIGluIHYyCj4gCj4g IGRyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jIHwgMzAgKysrKysrKysrKysr KysrKysrKysrKysrKysrKysrCj4gIDEgZmlsZSBjaGFuZ2VkLCAzMCBpbnNlcnRpb25zKCspCj4g Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jIGIv ZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL2R3LW1pcGktZHNpLmMKPiBpbmRleCA1OGNiOGFjZTJm ZTguLmNmM2NhNmIwY2JkYiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAv ZHctbWlwaS1kc2kuYwo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9kdy1taXBpLWRz aS5jCj4gQEAgLTEzLDYgKzEzLDcgQEAKPiAgI2luY2x1ZGUgPGxpbnV4L21vZHVsZS5oPgo+ICAj aW5jbHVkZSA8bGludXgvb2ZfZGV2aWNlLmg+Cj4gICNpbmNsdWRlIDxsaW51eC9yZWdtYXAuaD4K PiArI2luY2x1ZGUgPGxpbnV4L3Jlc2V0Lmg+Cj4gICNpbmNsdWRlIDxsaW51eC9tZmQvc3lzY29u Lmg+Cj4gICNpbmNsdWRlIDxkcm0vZHJtX2F0b21pY19oZWxwZXIuaD4KPiAgI2luY2x1ZGUgPGRy bS9kcm1fY3J0Yy5oPgo+IEBAIC0xMTI0LDYgKzExMjUsNyBAQCBzdGF0aWMgaW50IGR3X21pcGlf ZHNpX2JpbmQoc3RydWN0IGRldmljZSAqZGV2LCBzdHJ1Y3QgZGV2aWNlICptYXN0ZXIsCj4gIAkJ CW9mX21hdGNoX2RldmljZShkd19taXBpX2RzaV9kdF9pZHMsIGRldik7Cj4gIAljb25zdCBzdHJ1 Y3QgZHdfbWlwaV9kc2lfcGxhdF9kYXRhICpwZGF0YSA9IG9mX2lkLT5kYXRhOwo+ICAJc3RydWN0 IHBsYXRmb3JtX2RldmljZSAqcGRldiA9IHRvX3BsYXRmb3JtX2RldmljZShkZXYpOwo+ICsJc3Ry dWN0IHJlc2V0X2NvbnRyb2wgKmFwYl9yc3Q7Cj4gIAlzdHJ1Y3QgZHJtX2RldmljZSAqZHJtID0g ZGF0YTsKPiAgCXN0cnVjdCBkd19taXBpX2RzaSAqZHNpOwo+ICAJc3RydWN0IHJlc291cmNlICpy ZXM7Cj4gQEAgLTExNjIsNiArMTE2NCwzNCBAQCBzdGF0aWMgaW50IGR3X21pcGlfZHNpX2JpbmQo c3RydWN0IGRldmljZSAqZGV2LCBzdHJ1Y3QgZGV2aWNlICptYXN0ZXIsCj4gIAkJcmV0dXJuIHJl dDsKPiAgCX0KPiAgCj4gKwkvKgo+ICsJICogTm90ZSB0aGF0IHRoZSByZXNldCB3YXMgbm90IGRl ZmluZWQgaW4gdGhlIGluaXRpYWwgZGV2aWNlIHRyZWUsIHNvCj4gKwkgKiB3ZSBoYXZlIHRvIGJl IHByZXBhcmVkIGZvciBpdCBub3QgYmVpbmcgZm91bmQuCj4gKwkgKi8KPiArCWFwYl9yc3QgPSBk ZXZtX3Jlc2V0X2NvbnRyb2xfZ2V0KGRldiwgImFwYiIpOwo+ICsJaWYgKElTX0VSUihhcGJfcnN0 KSkgewo+ICsJCWlmIChQVFJfRVJSKGFwYl9yc3QpID09IC1FTk9ERVYpIHsKPiArCQkJYXBiX3Jz dCA9IE5VTEw7Cj4gKwkJfSBlbHNlIHsKPiArCQkJZGV2X2VycihkZXYsICJVbmFibGUgdG8gZ2V0 IHJlc2V0IGNvbnRyb2w6ICVkXG4iLCByZXQpOwo+ICsJCQlyZXR1cm4gUFRSX0VSUihhcGJfcnN0 KTsKPiArCQl9Cj4gKwl9Cj4gKwo+ICsJaWYgKGFwYl9yc3QpIHsKPiArCQlyZXQgPSBjbGtfcHJl cGFyZV9lbmFibGUoZHNpLT5wY2xrKTsKPiArCQlpZiAocmV0KSB7Cj4gKwkJCWRldl9lcnIoZGV2 LCAiJXM6IEZhaWxlZCB0byBlbmFibGUgcGNsa1xuIiwgX19mdW5jX18pOwo+ICsJCQlyZXR1cm4g cmV0Owo+ICsJCX0KPiArCj4gKwkJcmVzZXRfY29udHJvbF9hc3NlcnQoYXBiX3JzdCk7Cj4gKwkJ dXNsZWVwX3JhbmdlKDEwLCAyMCk7Cj4gKwkJcmVzZXRfY29udHJvbF9kZWFzc2VydChhcGJfcnN0 KTsKPiArCj4gKwkJY2xrX2Rpc2FibGVfdW5wcmVwYXJlKGRzaS0+cGNsayk7Cj4gKwl9Cj4gKwo+ ICAJcmV0ID0gY2xrX3ByZXBhcmVfZW5hYmxlKGRzaS0+cGxscmVmX2Nsayk7Cj4gIAlpZiAocmV0 KSB7Cj4gIAkJZGV2X2VycihkZXYsICIlczogRmFpbGVkIHRvIGVuYWJsZSBwbGxyZWZfY2xrXG4i LCBfX2Z1bmNfXyk7Cj4gLS0gCj4gMi4xMS4wLjE5Ny5nYjU1NmRlNS5kaXJ0eQo+IAo+IF9fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCj4gZHJpLWRldmVsIG1h aWxpbmcgbGlzdAo+IGRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKPiBodHRwczovL2xp c3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAoKLS0gClNlYW4g UGF1bCwgU29mdHdhcmUgRW5naW5lZXIsIEdvb2dsZSAvIENocm9taXVtIE9TCl9fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxp c3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNr dG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: seanpaul@chromium.org (Sean Paul) Date: Tue, 31 Jan 2017 14:28:07 -0500 Subject: [PATCH v3 23/24] drm/rockchip: dw-mipi-dsi: add reset control In-Reply-To: <20170129132444.25251-24-john@metanate.com> References: <20170129132444.25251-1-john@metanate.com> <20170129132444.25251-24-john@metanate.com> Message-ID: <20170131192807.GG20076@art_vandelay> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Sun, Jan 29, 2017 at 01:24:43PM +0000, John Keeping wrote: > In order to fully reset the state of the MIPI controller we must assert > this reset. > > This is slightly more complicated than it could be in order to maintain > compatibility with device trees that do not specify the reset property. > I always find it a little grating to see a device managed resource given to a local variable that is used immediately and only once. However, I think this might just be one of my twitches. So now that I've aired my grievance, Reviewed-by: Sean Paul > Signed-off-by: John Keeping > Reviewed-by: Chris Zhong > --- > v3: > - Add Chris' Reviewed-by > Unchanged in v2 > > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index 58cb8ace2fe8..cf3ca6b0cbdb 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -13,6 +13,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -1124,6 +1125,7 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, > of_match_device(dw_mipi_dsi_dt_ids, dev); > const struct dw_mipi_dsi_plat_data *pdata = of_id->data; > struct platform_device *pdev = to_platform_device(dev); > + struct reset_control *apb_rst; > struct drm_device *drm = data; > struct dw_mipi_dsi *dsi; > struct resource *res; > @@ -1162,6 +1164,34 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, > return ret; > } > > + /* > + * Note that the reset was not defined in the initial device tree, so > + * we have to be prepared for it not being found. > + */ > + apb_rst = devm_reset_control_get(dev, "apb"); > + if (IS_ERR(apb_rst)) { > + if (PTR_ERR(apb_rst) == -ENODEV) { > + apb_rst = NULL; > + } else { > + dev_err(dev, "Unable to get reset control: %d\n", ret); > + return PTR_ERR(apb_rst); > + } > + } > + > + if (apb_rst) { > + ret = clk_prepare_enable(dsi->pclk); > + if (ret) { > + dev_err(dev, "%s: Failed to enable pclk\n", __func__); > + return ret; > + } > + > + reset_control_assert(apb_rst); > + usleep_range(10, 20); > + reset_control_deassert(apb_rst); > + > + clk_disable_unprepare(dsi->pclk); > + } > + > ret = clk_prepare_enable(dsi->pllref_clk); > if (ret) { > dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__); > -- > 2.11.0.197.gb556de5.dirty > > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Sean Paul, Software Engineer, Google / Chromium OS From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752189AbdAaT2V (ORCPT ); Tue, 31 Jan 2017 14:28:21 -0500 Received: from mail-qk0-f176.google.com ([209.85.220.176]:35278 "EHLO mail-qk0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752130AbdAaT2K (ORCPT ); Tue, 31 Jan 2017 14:28:10 -0500 Date: Tue, 31 Jan 2017 14:28:07 -0500 From: Sean Paul To: John Keeping Cc: Mark Yao , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Chris Zhong , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 23/24] drm/rockchip: dw-mipi-dsi: add reset control Message-ID: <20170131192807.GG20076@art_vandelay> References: <20170129132444.25251-1-john@metanate.com> <20170129132444.25251-24-john@metanate.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170129132444.25251-24-john@metanate.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Jan 29, 2017 at 01:24:43PM +0000, John Keeping wrote: > In order to fully reset the state of the MIPI controller we must assert > this reset. > > This is slightly more complicated than it could be in order to maintain > compatibility with device trees that do not specify the reset property. > I always find it a little grating to see a device managed resource given to a local variable that is used immediately and only once. However, I think this might just be one of my twitches. So now that I've aired my grievance, Reviewed-by: Sean Paul > Signed-off-by: John Keeping > Reviewed-by: Chris Zhong > --- > v3: > - Add Chris' Reviewed-by > Unchanged in v2 > > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index 58cb8ace2fe8..cf3ca6b0cbdb 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -13,6 +13,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -1124,6 +1125,7 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, > of_match_device(dw_mipi_dsi_dt_ids, dev); > const struct dw_mipi_dsi_plat_data *pdata = of_id->data; > struct platform_device *pdev = to_platform_device(dev); > + struct reset_control *apb_rst; > struct drm_device *drm = data; > struct dw_mipi_dsi *dsi; > struct resource *res; > @@ -1162,6 +1164,34 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, > return ret; > } > > + /* > + * Note that the reset was not defined in the initial device tree, so > + * we have to be prepared for it not being found. > + */ > + apb_rst = devm_reset_control_get(dev, "apb"); > + if (IS_ERR(apb_rst)) { > + if (PTR_ERR(apb_rst) == -ENODEV) { > + apb_rst = NULL; > + } else { > + dev_err(dev, "Unable to get reset control: %d\n", ret); > + return PTR_ERR(apb_rst); > + } > + } > + > + if (apb_rst) { > + ret = clk_prepare_enable(dsi->pclk); > + if (ret) { > + dev_err(dev, "%s: Failed to enable pclk\n", __func__); > + return ret; > + } > + > + reset_control_assert(apb_rst); > + usleep_range(10, 20); > + reset_control_deassert(apb_rst); > + > + clk_disable_unprepare(dsi->pclk); > + } > + > ret = clk_prepare_enable(dsi->pllref_clk); > if (ret) { > dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__); > -- > 2.11.0.197.gb556de5.dirty > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Sean Paul, Software Engineer, Google / Chromium OS