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[81.231.233.234]) by smtp.gmail.com with ESMTPSA id m18sm350537lfe.45.2017.02.06.07.06.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 06 Feb 2017 07:06:34 -0800 (PST) Date: Mon, 6 Feb 2017 16:06:33 +0100 From: "Edgar E. Iglesias" To: Peter Maydell Message-ID: <20170206150633.GQ9606@toto> References: <1486144135-4894-1-git-send-email-peter.maydell@linaro.org> <1486144135-4894-3-git-send-email-peter.maydell@linaro.org> <20170204143132.GP9606@toto> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:4010:c07::243 Subject: Re: [Qemu-arm] [PATCH v2 2/2] target/arm: A32, T32: Create Instruction Syndromes for Data Aborts X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm , QEMU Developers , "patches@linaro.org" Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: 4+qoW9mtfeb5 On Mon, Feb 06, 2017 at 02:53:49PM +0000, Peter Maydell wrote: > On 4 February 2017 at 14:31, Edgar E. Iglesias wrote: > > On Fri, Feb 03, 2017 at 05:48:55PM +0000, Peter Maydell wrote: > >> Add support for generating the ISS (Instruction Specific Syndrome) > >> for Data Abort exceptions taken from AArch32. These syndromes are > >> used by hypervisors for example to trap and emulate memory accesses. > >> > >> This is the equivalent for AArch32 guests of the work done for AArch64 > >> guests in commit aaa1f954d4cab243. > > >> +static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) > >> +{ > >> + /* We don't need to save all of the syndrome so we mask and shift > >> + * out uneeded bits to help the sleb128 encoder do a better job. > >> + */ > >> + syn &= ARM_INSN_START_WORD2_MASK; > >> + syn >>= ARM_INSN_START_WORD2_SHIFT; > >> + > >> + /* We check and clear insn_start_idx to catch multiple updates. */ > >> + assert(s->insn_start_idx != 0); > >> + tcg_set_insn_param(s->insn_start_idx, 2, syn); > >> + s->insn_start_idx = 0; > >> +} > > > > Could we move this into translate.h and share it with translate-a64.c? > > Sure; I'll just squash that change into this patch and put the > results into the target-arm queue, rather than burdening the > list with a v3 respin, if that's OK. Sounds good, thanks! Cheers, Edgar From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58551) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1caksS-0008GU-8O for qemu-devel@nongnu.org; Mon, 06 Feb 2017 10:06:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1caksR-0008FJ-EQ for qemu-devel@nongnu.org; Mon, 06 Feb 2017 10:06:48 -0500 Date: Mon, 6 Feb 2017 16:06:33 +0100 From: "Edgar E. Iglesias" Message-ID: <20170206150633.GQ9606@toto> References: <1486144135-4894-1-git-send-email-peter.maydell@linaro.org> <1486144135-4894-3-git-send-email-peter.maydell@linaro.org> <20170204143132.GP9606@toto> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH v2 2/2] target/arm: A32, T32: Create Instruction Syndromes for Data Aborts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-arm , QEMU Developers , "patches@linaro.org" On Mon, Feb 06, 2017 at 02:53:49PM +0000, Peter Maydell wrote: > On 4 February 2017 at 14:31, Edgar E. Iglesias wrote: > > On Fri, Feb 03, 2017 at 05:48:55PM +0000, Peter Maydell wrote: > >> Add support for generating the ISS (Instruction Specific Syndrome) > >> for Data Abort exceptions taken from AArch32. These syndromes are > >> used by hypervisors for example to trap and emulate memory accesses. > >> > >> This is the equivalent for AArch32 guests of the work done for AArch64 > >> guests in commit aaa1f954d4cab243. > > >> +static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) > >> +{ > >> + /* We don't need to save all of the syndrome so we mask and shift > >> + * out uneeded bits to help the sleb128 encoder do a better job. > >> + */ > >> + syn &= ARM_INSN_START_WORD2_MASK; > >> + syn >>= ARM_INSN_START_WORD2_SHIFT; > >> + > >> + /* We check and clear insn_start_idx to catch multiple updates. */ > >> + assert(s->insn_start_idx != 0); > >> + tcg_set_insn_param(s->insn_start_idx, 2, syn); > >> + s->insn_start_idx = 0; > >> +} > > > > Could we move this into translate.h and share it with translate-a64.c? > > Sure; I'll just squash that change into this patch and put the > results into the target-arm queue, rather than burdening the > list with a v3 respin, if that's OK. Sounds good, thanks! Cheers, Edgar