From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Shevchenko Date: Tue, 14 Feb 2017 17:47:14 +0300 Subject: [U-Boot] [PATCH v1 3/3] x86: Intel MID platforms has no microcode update In-Reply-To: <20170214144714.96516-1-andriy.shevchenko@linux.intel.com> References: <20170214144714.96516-1-andriy.shevchenko@linux.intel.com> Message-ID: <20170214144714.96516-3-andriy.shevchenko@linux.intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de There is no microcode update available for SoCs used on Intel MID platforms. Use conditional to bypass it. Signed-off-by: Andy Shevchenko --- arch/x86/cpu/mp_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index 988073cc79..4e2f000f75 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -248,7 +248,7 @@ static int load_sipi_vector(atomic_t **ap_countp, int num_cpus) if (!stack) return -ENOMEM; params->stack_top = (u32)(stack + size); -#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) +#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) && !defined(CONFIG_INTEL_MID) params->microcode_ptr = ucode_base; debug("Microcode at %x\n", params->microcode_ptr); #endif -- 2.11.0