From: Stephen Boyd <sboyd@codeaurora.org>
To: Chris Brandt <chris.brandt@renesas.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>,
Michael Turquette <mturquette@baylibre.com>,
Simon Horman <horms+renesas@verge.net.au>,
linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH v3] clk: renesas: mstp: ensure register writes complete
Date: Tue, 14 Feb 2017 11:00:48 -0800 [thread overview]
Message-ID: <20170214190048.GU25384@codeaurora.org> (raw)
In-Reply-To: <20170214160805.20156-1-chris.brandt@renesas.com>
On 02/14, Chris Brandt wrote:
> When there is no status bit, it is possible for the clock enable/disable
> operation to have not completed by the time the driver code resumes
> execution. This is due to the fact that write operations are sometimes
> queued and delayed internally. Doing a read ensures the write operations
> has completed.
>
> Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi")
> Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
prev parent reply other threads:[~2017-02-14 19:00 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-14 16:08 [PATCH v3] clk: renesas: mstp: ensure register writes complete Chris Brandt
2017-02-14 19:00 ` Stephen Boyd [this message]
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