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From: Tvrtko Ursulin <tursulin@ursulin.net>
To: Intel-gfx@lists.freedesktop.org
Subject: [PATCH 2/2] drm/i915: Consolidate gen8_emit_pipe_control
Date: Wed, 15 Feb 2017 16:06:34 +0000	[thread overview]
Message-ID: <20170215160634.8894-2-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <20170215160634.8894-1-tvrtko.ursulin@linux.intel.com>

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

We have a few open coded instances in the execlists code and an
almost suitable helper in intel_ringbuf.c

We can consolidate to a single helper if we change the existing
helper to emit directly to ring buffer memory and move the space
reservation outside it.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c        | 77 +++++++++++----------------------
 drivers/gpu/drm/i915/intel_ringbuffer.c | 45 +++++++------------
 drivers/gpu/drm/i915/intel_ringbuffer.h | 12 +++++
 3 files changed, 53 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f6537d14d247..ec79f275c61a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -918,12 +918,10 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
 	*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
 	*batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
 
-	*batch++ = GFX_OP_PIPE_CONTROL(6);
-	*batch++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_DC_FLUSH_ENABLE;
-	*batch++ = 0;
-	*batch++ = 0;
-	*batch++ = 0;
-	*batch++ = 0;
+	batch = gen8_emit_pipe_control(batch,
+				       PIPE_CONTROL_CS_STALL |
+				       PIPE_CONTROL_DC_FLUSH_ENABLE,
+				       0);
 
 	*batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
 	*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
@@ -957,15 +955,15 @@ static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
 	if (IS_BROADWELL(engine->i915))
 		batch = gen8_emit_flush_coherentl3_wa(engine, batch);
 
-	*batch++ = GFX_OP_PIPE_CONTROL(6);
-	*batch++ = PIPE_CONTROL_FLUSH_L3 | PIPE_CONTROL_GLOBAL_GTT_IVB |
-		   PIPE_CONTROL_CS_STALL | PIPE_CONTROL_QW_WRITE;
 	/* WaClearSlmSpaceAtContextSwitch:bdw,chv */
 	/* Actual scratch location is at 128 bytes offset */
-	*batch++ = i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
-	*batch++ = 0;
-	*batch++ = 0;
-	*batch++ = 0;
+	batch = gen8_emit_pipe_control(batch,
+				       PIPE_CONTROL_FLUSH_L3 |
+				       PIPE_CONTROL_GLOBAL_GTT_IVB |
+				       PIPE_CONTROL_CS_STALL |
+				       PIPE_CONTROL_QW_WRITE,
+				       i915_ggtt_offset(engine->scratch) +
+				       2 * CACHELINE_BYTES);
 
 	/* Pad to end of cacheline */
 	while ((unsigned long)batch % CACHELINE_BYTES)
@@ -1013,14 +1011,13 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
 	/* WaClearSlmSpaceAtContextSwitch:kbl */
 	/* Actual scratch location is at 128 bytes offset */
 	if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
-		*batch++ = GFX_OP_PIPE_CONTROL(6);
-		*batch++ = PIPE_CONTROL_FLUSH_L3 | PIPE_CONTROL_GLOBAL_GTT_IVB |
-			   PIPE_CONTROL_CS_STALL | PIPE_CONTROL_QW_WRITE;
-		*batch++ = i915_ggtt_offset(engine->scratch) +
-			   2 * CACHELINE_BYTES;
-		*batch++ = 0;
-		*batch++ = 0;
-		*batch++ = 0;
+		batch = gen8_emit_pipe_control(batch,
+					       PIPE_CONTROL_FLUSH_L3 |
+					       PIPE_CONTROL_GLOBAL_GTT_IVB |
+					       PIPE_CONTROL_CS_STALL |
+					       PIPE_CONTROL_QW_WRITE,
+					       i915_ggtt_offset(engine->scratch)
+					       + 2 * CACHELINE_BYTES);
 	}
 
 	/* WaMediaPoolStateCmdInWABB:bxt,glk */
@@ -1450,39 +1447,17 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
 	if (IS_ERR(cs))
 		return PTR_ERR(cs);
 
-	if (vf_flush_wa) {
-		*cs++ = GFX_OP_PIPE_CONTROL(6);
-		*cs++ = 0;
-		*cs++ = 0;
-		*cs++ = 0;
-		*cs++ = 0;
-		*cs++ = 0;
-	}
+	if (vf_flush_wa)
+		cs = gen8_emit_pipe_control(cs, 0, 0);
 
-	if (dc_flush_wa) {
-		*cs++ = GFX_OP_PIPE_CONTROL(6);
-		*cs++ = PIPE_CONTROL_DC_FLUSH_ENABLE;
-		*cs++ = 0;
-		*cs++ = 0;
-		*cs++ = 0;
-		*cs++ = 0;
-	}
+	if (dc_flush_wa)
+		cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
+					    0);
 
-	*cs++ = GFX_OP_PIPE_CONTROL(6);
-	*cs++ = flags;
-	*cs++ = scratch_addr;
-	*cs++ = 0;
-	*cs++ = 0;
-	*cs++ = 0;
+	cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
 
-	if (dc_flush_wa) {
-		*cs++ = GFX_OP_PIPE_CONTROL(6);
-		*cs++ = PIPE_CONTROL_CS_STALL;
-		*cs++ = 0;
-		*cs++ = 0;
-		*cs++ = 0;
-		*cs++ = 0;
-	}
+	if (dc_flush_wa)
+		cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
 
 	intel_ring_advance(request, cs);
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f7499829ecc2..a359527948b9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -334,35 +334,16 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
 }
 
 static int
-gen8_emit_pipe_control(struct drm_i915_gem_request *req,
-		       u32 flags, u32 scratch_addr)
+gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
 {
+	u32 flags;
 	u32 *cs;
 
-	cs = intel_ring_begin(req, 6);
+	cs = intel_ring_begin(req, mode & EMIT_INVALIDATE ? 12 : 6);
 	if (IS_ERR(cs))
 		return PTR_ERR(cs);
 
-	*cs++ = GFX_OP_PIPE_CONTROL(6);
-	*cs++ = flags;
-	*cs++ = scratch_addr;
-	*cs++ = 0;
-	*cs++ = 0;
-	*cs++ = 0;
-	intel_ring_advance(req, cs);
-
-	return 0;
-}
-
-static int
-gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
-{
-	u32 scratch_addr =
-		i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES;
-	u32 flags = 0;
-	int ret;
-
-	flags |= PIPE_CONTROL_CS_STALL;
+	flags = PIPE_CONTROL_CS_STALL;
 
 	if (mode & EMIT_FLUSH) {
 		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
@@ -381,15 +362,19 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
 		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 
 		/* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
-		ret = gen8_emit_pipe_control(req,
-					     PIPE_CONTROL_CS_STALL |
-					     PIPE_CONTROL_STALL_AT_SCOREBOARD,
-					     0);
-		if (ret)
-			return ret;
+		cs = gen8_emit_pipe_control(cs,
+					    PIPE_CONTROL_CS_STALL |
+					    PIPE_CONTROL_STALL_AT_SCOREBOARD,
+					    0);
 	}
 
-	return gen8_emit_pipe_control(req, flags, scratch_addr);
+	cs = gen8_emit_pipe_control(cs, flags,
+				    i915_ggtt_offset(req->engine->scratch) +
+				    2 * CACHELINE_BYTES);
+
+	intel_ring_advance(req, cs);
+
+	return 0;
 }
 
 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 16714096810d..de8b27548dcb 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -632,4 +632,16 @@ void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine);
 void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
 unsigned int intel_breadcrumbs_busy(struct drm_i915_private *i915);
 
+static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
+{
+	static const u32 pc6[6] = { GFX_OP_PIPE_CONTROL(6), 0, 0, 0, 0, 0 };
+
+	memcpy(batch, pc6, sizeof(pc6));
+
+	batch[1] = flags;
+	batch[2] = offset;
+
+	return batch + 6;
+}
+
 #endif /* _INTEL_RINGBUFFER_H_ */
-- 
2.9.3

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  reply	other threads:[~2017-02-15 16:06 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-15 16:06 [PATCH 1/2] drm/i915: Tidy workaround batch buffer emission Tvrtko Ursulin
2017-02-15 16:06 ` Tvrtko Ursulin [this message]
2017-02-15 16:33   ` [PATCH 2/2] drm/i915: Consolidate gen8_emit_pipe_control Chris Wilson
2017-02-16  7:53     ` Tvrtko Ursulin
2017-02-16  8:12       ` Chris Wilson
2017-02-15 21:09   ` Chris Wilson
2017-02-15 18:52 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Tidy workaround batch buffer emission Patchwork
2017-02-15 21:18 ` [PATCH 1/2] " Chris Wilson
2017-02-16  7:59   ` Tvrtko Ursulin
2017-02-16  8:22     ` Chris Wilson
2017-02-16 12:20 ` ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork

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