diff for duplicates of <20170215211958.GC29730@linaro.org> diff --git a/a/1.txt b/N1/1.txt index 1ab4f3b..5c0af52 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -4,7 +4,7 @@ On Mon, Feb 13, 2017 at 02:11:38PM +0800, Leo Yan wrote: Bindings for the coresight debug driver... > -> Signed-off-by: Leo Yan <leo.yan@linaro.org> +> Signed-off-by: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > --- > .../boot/dts/hisilicon/hikey_6220_coresight.dtsi | 73 ++++++++++++++++++++++ > 1 file changed, 73 insertions(+) @@ -18,9 +18,9 @@ Bindings for the coresight debug driver... > compatible = "arm,amba-bus"; > ranges; > + -> + debug at 0,f6590000 { +> + debug@0,f6590000 { -Simply use "debug at f6590000", the "0," isn't required. +Simply use "debug@f6590000", the "0," isn't required. > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf6590000 0 0x1000>; @@ -33,7 +33,7 @@ What is the "default_enable" for ? > + cpu = <&cpu0>; > + }; > + -> + debug at 1,f6592000 { +> + debug@1,f6592000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf6592000 0 0x1000>; > + default_enable; @@ -42,7 +42,7 @@ What is the "default_enable" for ? > + cpu = <&cpu1>; > + }; > + -> + debug at 2,f6594000 { +> + debug@2,f6594000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf6594000 0 0x1000>; > + default_enable; @@ -51,7 +51,7 @@ What is the "default_enable" for ? > + cpu = <&cpu2>; > + }; > + -> + debug at 3,f6596000 { +> + debug@3,f6596000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf6596000 0 0x1000>; > + default_enable; @@ -60,7 +60,7 @@ What is the "default_enable" for ? > + cpu = <&cpu3>; > + }; > + -> + debug at 4,f65d0000 { +> + debug@4,f65d0000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf65d0000 0 0x1000>; > + default_enable; @@ -69,7 +69,7 @@ What is the "default_enable" for ? > + cpu = <&cpu4>; > + }; > + -> + debug at 5,f65d2000 { +> + debug@5,f65d2000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf65d2000 0 0x1000>; > + default_enable; @@ -78,7 +78,7 @@ What is the "default_enable" for ? > + cpu = <&cpu5>; > + }; > + -> + debug at 6,f65d4000 { +> + debug@6,f65d4000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf65d4000 0 0x1000>; > + default_enable; @@ -87,7 +87,7 @@ What is the "default_enable" for ? > + cpu = <&cpu6>; > + }; > + -> + debug at 7,f65d6000 { +> + debug@7,f65d6000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf65d6000 0 0x1000>; > + default_enable; @@ -96,9 +96,13 @@ What is the "default_enable" for ? > + cpu = <&cpu7>; > + }; > + -> etm at 0,f659c000 { +> etm@0,f659c000 { > compatible = "arm,coresight-etm4x","arm,primecell"; > reg = <0 0xf659c000 0 0x1000>; > -- > 2.7.4 -> +> +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 2dd7d0d..deb280b 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,19 @@ "ref\01486966298-16767-1-git-send-email-leo.yan@linaro.org\0" "ref\01486966298-16767-4-git-send-email-leo.yan@linaro.org\0" - "From\0mathieu.poirier@linaro.org (Mathieu Poirier)\0" - "Subject\0[PATCH RFC 3/3] arm64: dts: register Hi6220's coresight debug module\0" + "ref\01486966298-16767-4-git-send-email-leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org\0" + "From\0Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" + "Subject\0Re: [PATCH RFC 3/3] arm64: dts: register Hi6220's coresight debug module\0" "Date\0Wed, 15 Feb 2017 14:19:58 -0700\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" + "Cc\0Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>" + Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> + Wei Xu <xuwei5-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> + Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org> + Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " Daniel Thompson <daniel.thompson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" "\00:1\0" "b\0" "On Mon, Feb 13, 2017 at 02:11:38PM +0800, Leo Yan wrote:\n" @@ -12,7 +22,7 @@ "Bindings for the coresight debug driver...\n" "\n" "> \n" - "> Signed-off-by: Leo Yan <leo.yan@linaro.org>\n" + "> Signed-off-by: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\n" "> ---\n" "> .../boot/dts/hisilicon/hikey_6220_coresight.dtsi | 73 ++++++++++++++++++++++\n" "> 1 file changed, 73 insertions(+)\n" @@ -26,9 +36,9 @@ "> \t\tcompatible = \"arm,amba-bus\";\n" "> \t\tranges;\n" "> +\n" - "> +\t\tdebug at 0,f6590000 {\n" + "> +\t\tdebug@0,f6590000 {\n" "\n" - "Simply use \"debug at f6590000\", the \"0,\" isn't required.\n" + "Simply use \"debug@f6590000\", the \"0,\" isn't required.\n" "\n" "> +\t\t\tcompatible = \"arm,coresight-debug\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf6590000 0 0x1000>;\n" @@ -41,7 +51,7 @@ "> +\t\t\tcpu = <&cpu0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tdebug at 1,f6592000 {\n" + "> +\t\tdebug@1,f6592000 {\n" "> +\t\t\tcompatible = \"arm,coresight-debug\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf6592000 0 0x1000>;\n" "> +\t\t\tdefault_enable;\n" @@ -50,7 +60,7 @@ "> +\t\t\tcpu = <&cpu1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tdebug at 2,f6594000 {\n" + "> +\t\tdebug@2,f6594000 {\n" "> +\t\t\tcompatible = \"arm,coresight-debug\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf6594000 0 0x1000>;\n" "> +\t\t\tdefault_enable;\n" @@ -59,7 +69,7 @@ "> +\t\t\tcpu = <&cpu2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tdebug at 3,f6596000 {\n" + "> +\t\tdebug@3,f6596000 {\n" "> +\t\t\tcompatible = \"arm,coresight-debug\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf6596000 0 0x1000>;\n" "> +\t\t\tdefault_enable;\n" @@ -68,7 +78,7 @@ "> +\t\t\tcpu = <&cpu3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tdebug at 4,f65d0000 {\n" + "> +\t\tdebug@4,f65d0000 {\n" "> +\t\t\tcompatible = \"arm,coresight-debug\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf65d0000 0 0x1000>;\n" "> +\t\t\tdefault_enable;\n" @@ -77,7 +87,7 @@ "> +\t\t\tcpu = <&cpu4>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tdebug at 5,f65d2000 {\n" + "> +\t\tdebug@5,f65d2000 {\n" "> +\t\t\tcompatible = \"arm,coresight-debug\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf65d2000 0 0x1000>;\n" "> +\t\t\tdefault_enable;\n" @@ -86,7 +96,7 @@ "> +\t\t\tcpu = <&cpu5>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tdebug at 6,f65d4000 {\n" + "> +\t\tdebug@6,f65d4000 {\n" "> +\t\t\tcompatible = \"arm,coresight-debug\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf65d4000 0 0x1000>;\n" "> +\t\t\tdefault_enable;\n" @@ -95,7 +105,7 @@ "> +\t\t\tcpu = <&cpu6>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tdebug at 7,f65d6000 {\n" + "> +\t\tdebug@7,f65d6000 {\n" "> +\t\t\tcompatible = \"arm,coresight-debug\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf65d6000 0 0x1000>;\n" "> +\t\t\tdefault_enable;\n" @@ -104,11 +114,15 @@ "> +\t\t\tcpu = <&cpu7>;\n" "> +\t\t};\n" "> +\n" - "> \t\tetm at 0,f659c000 {\n" + "> \t\tetm@0,f659c000 {\n" "> \t\t\tcompatible = \"arm,coresight-etm4x\",\"arm,primecell\";\n" "> \t\t\treg = <0 0xf659c000 0 0x1000>;\n" "> -- \n" "> 2.7.4\n" - > + "> \n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -cc9476218dd8f68c04c2f04c501372d4bc3e73d480241df93896b7f9b108274e +4ff91d7d1ab20db867761e5ed5ef651816cee6afa85858b49e071c0a65579afe
diff --git a/a/1.txt b/N2/1.txt index 1ab4f3b..58677ce 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -18,9 +18,9 @@ Bindings for the coresight debug driver... > compatible = "arm,amba-bus"; > ranges; > + -> + debug at 0,f6590000 { +> + debug@0,f6590000 { -Simply use "debug at f6590000", the "0," isn't required. +Simply use "debug@f6590000", the "0," isn't required. > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf6590000 0 0x1000>; @@ -33,7 +33,7 @@ What is the "default_enable" for ? > + cpu = <&cpu0>; > + }; > + -> + debug at 1,f6592000 { +> + debug@1,f6592000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf6592000 0 0x1000>; > + default_enable; @@ -42,7 +42,7 @@ What is the "default_enable" for ? > + cpu = <&cpu1>; > + }; > + -> + debug at 2,f6594000 { +> + debug@2,f6594000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf6594000 0 0x1000>; > + default_enable; @@ -51,7 +51,7 @@ What is the "default_enable" for ? > + cpu = <&cpu2>; > + }; > + -> + debug at 3,f6596000 { +> + debug@3,f6596000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf6596000 0 0x1000>; > + default_enable; @@ -60,7 +60,7 @@ What is the "default_enable" for ? > + cpu = <&cpu3>; > + }; > + -> + debug at 4,f65d0000 { +> + debug@4,f65d0000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf65d0000 0 0x1000>; > + default_enable; @@ -69,7 +69,7 @@ What is the "default_enable" for ? > + cpu = <&cpu4>; > + }; > + -> + debug at 5,f65d2000 { +> + debug@5,f65d2000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf65d2000 0 0x1000>; > + default_enable; @@ -78,7 +78,7 @@ What is the "default_enable" for ? > + cpu = <&cpu5>; > + }; > + -> + debug at 6,f65d4000 { +> + debug@6,f65d4000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf65d4000 0 0x1000>; > + default_enable; @@ -87,7 +87,7 @@ What is the "default_enable" for ? > + cpu = <&cpu6>; > + }; > + -> + debug at 7,f65d6000 { +> + debug@7,f65d6000 { > + compatible = "arm,coresight-debug","arm,primecell"; > + reg = <0 0xf65d6000 0 0x1000>; > + default_enable; @@ -96,7 +96,7 @@ What is the "default_enable" for ? > + cpu = <&cpu7>; > + }; > + -> etm at 0,f659c000 { +> etm@0,f659c000 { > compatible = "arm,coresight-etm4x","arm,primecell"; > reg = <0 0xf659c000 0 0x1000>; > -- diff --git a/a/content_digest b/N2/content_digest index 2dd7d0d..a43fc17 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,9 +1,18 @@ "ref\01486966298-16767-1-git-send-email-leo.yan@linaro.org\0" "ref\01486966298-16767-4-git-send-email-leo.yan@linaro.org\0" - "From\0mathieu.poirier@linaro.org (Mathieu Poirier)\0" - "Subject\0[PATCH RFC 3/3] arm64: dts: register Hi6220's coresight debug module\0" + "From\0Mathieu Poirier <mathieu.poirier@linaro.org>\0" + "Subject\0Re: [PATCH RFC 3/3] arm64: dts: register Hi6220's coresight debug module\0" "Date\0Wed, 15 Feb 2017 14:19:58 -0700\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Leo Yan <leo.yan@linaro.org>\0" + "Cc\0Rob Herring <robh+dt@kernel.org>" + Mark Rutland <mark.rutland@arm.com> + Wei Xu <xuwei5@hisilicon.com> + Catalin Marinas <catalin.marinas@arm.com> + Will Deacon <will.deacon@arm.com> + linux-arm-kernel@lists.infradead.org + devicetree@vger.kernel.org + linux-kernel@vger.kernel.org + " Daniel Thompson <daniel.thompson@linaro.org>\0" "\00:1\0" "b\0" "On Mon, Feb 13, 2017 at 02:11:38PM +0800, Leo Yan wrote:\n" @@ -26,9 +35,9 @@ "> \t\tcompatible = \"arm,amba-bus\";\n" "> \t\tranges;\n" "> +\n" - "> +\t\tdebug at 0,f6590000 {\n" + "> +\t\tdebug@0,f6590000 {\n" "\n" - "Simply use \"debug at f6590000\", the \"0,\" isn't required.\n" + "Simply use \"debug@f6590000\", the \"0,\" isn't required.\n" "\n" "> +\t\t\tcompatible = \"arm,coresight-debug\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf6590000 0 0x1000>;\n" @@ -41,7 +50,7 @@ "> +\t\t\tcpu = <&cpu0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tdebug at 1,f6592000 {\n" + "> +\t\tdebug@1,f6592000 {\n" "> +\t\t\tcompatible = \"arm,coresight-debug\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf6592000 0 0x1000>;\n" "> +\t\t\tdefault_enable;\n" @@ -50,7 +59,7 @@ "> +\t\t\tcpu = <&cpu1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tdebug at 2,f6594000 {\n" + "> +\t\tdebug@2,f6594000 {\n" "> +\t\t\tcompatible = \"arm,coresight-debug\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf6594000 0 0x1000>;\n" "> +\t\t\tdefault_enable;\n" @@ -59,7 +68,7 @@ "> +\t\t\tcpu = <&cpu2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tdebug at 3,f6596000 {\n" + "> +\t\tdebug@3,f6596000 {\n" "> +\t\t\tcompatible = \"arm,coresight-debug\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf6596000 0 0x1000>;\n" "> +\t\t\tdefault_enable;\n" @@ -68,7 +77,7 @@ "> +\t\t\tcpu = <&cpu3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tdebug at 4,f65d0000 {\n" + "> +\t\tdebug@4,f65d0000 {\n" "> +\t\t\tcompatible = \"arm,coresight-debug\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf65d0000 0 0x1000>;\n" "> +\t\t\tdefault_enable;\n" @@ -77,7 +86,7 @@ "> +\t\t\tcpu = <&cpu4>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tdebug at 5,f65d2000 {\n" + "> +\t\tdebug@5,f65d2000 {\n" "> +\t\t\tcompatible = \"arm,coresight-debug\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf65d2000 0 0x1000>;\n" "> +\t\t\tdefault_enable;\n" @@ -86,7 +95,7 @@ "> +\t\t\tcpu = <&cpu5>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tdebug at 6,f65d4000 {\n" + "> +\t\tdebug@6,f65d4000 {\n" "> +\t\t\tcompatible = \"arm,coresight-debug\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf65d4000 0 0x1000>;\n" "> +\t\t\tdefault_enable;\n" @@ -95,7 +104,7 @@ "> +\t\t\tcpu = <&cpu6>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tdebug at 7,f65d6000 {\n" + "> +\t\tdebug@7,f65d6000 {\n" "> +\t\t\tcompatible = \"arm,coresight-debug\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf65d6000 0 0x1000>;\n" "> +\t\t\tdefault_enable;\n" @@ -104,11 +113,11 @@ "> +\t\t\tcpu = <&cpu7>;\n" "> +\t\t};\n" "> +\n" - "> \t\tetm at 0,f659c000 {\n" + "> \t\tetm@0,f659c000 {\n" "> \t\t\tcompatible = \"arm,coresight-etm4x\",\"arm,primecell\";\n" "> \t\t\treg = <0 0xf659c000 0 0x1000>;\n" "> -- \n" "> 2.7.4\n" > -cc9476218dd8f68c04c2f04c501372d4bc3e73d480241df93896b7f9b108274e +63b5b0d53093bcddcb8e0042cae22c68dede3033d1cb2500ed013b60f139c082
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