Re: [PATCH] drm/i915: Only apply legacy PDE overflow detection to 3lvl machines

From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org, Mika Kuoppala <mika.kuoppala@intel.com>
Subject: Re: [PATCH] drm/i915: Only apply legacy PDE overflow detection to 3lvl machines
Date: Fri, 17 Feb 2017 16:07:50 +0200	[thread overview]
Message-ID: <20170217140750.GT31595@intel.com> (raw)
In-Reply-To: <20170217135909.14596-1-chris@chris-wilson.co.uk>

On Fri, Feb 17, 2017 at 01:59:09PM +0000, Chris Wilson wrote:
> Prevent the overflow check from firing on machines with the full 4lvl
> page tables, that are not restricted to GEN8_LEGACY_PDES.
> 
> Fixes: 894ccebee2b0 ("drm/i915: Micro-optimise gen8_ppgtt_insert_entries()")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 1f281554e4c9..65cadc09b56e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -854,7 +854,8 @@ gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt,
>  					break;
>  				}
>  
> -				GEM_BUG_ON(pdpe > GEN8_LEGACY_PDPES);
> +				GEM_BUG_ON(!i915_vm_is_48bit(&ppgtt->base) &&
> +					   pdpe > GEN8_LEGACY_PDPES);

Should that be >= ?

>  				pd = pdp->page_directory[pdpe];
>  				pde = 0;
>  			}
> -- 
> 2.11.0
> 
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-- 
Ville Syrjälä
Intel OTC
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