Re: [PATCH 3/3] drm/i915: reorganize the get_cdclk assignment

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Mon, Feb 20, 2017 at 05:00:42PM -0300, Paulo Zanoni wrote:
> Possible problems of the current if-ladder:
>   - It's a huge if ladder with almost a different check for each of
>     our platforms.
>   - It mixes 3 different types of checks: IS_GENX, IS_PLATFORM and
>     IS_GROUP_OF_PLATFORMS.
>   - As demonstrated by the recent IS_G4X commit, it's not easy to be
>     sure if a platform down on the list isn't also checked earlier.
>   - As demonstrated by the WARN at the end, it's not easy to be sure
>     if we're actually checking for every single platform.
> 
> Possible advantages of the new switch statement:
>   - It may be easier for the compiler to optimize stuff (I didn't
>     check this), especially since the values are labels of an enum.
>   - The compiler will tell us in case we miss some platform.
>   - All platforms are explicitly there instead of maybe hidden in some
>     check for a certain group of platforms such as IS_GEN9_BC.
> 
> Possible disadvantages with the new code:
>   - A few lines bigger.
> 
> v2: Don't unsort the list. Now the list almost matches the enum
> definition, with the exception of CHV, KBL and GLK, which are listed
> along their predecessors (Ville).
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 105 +++++++++++++++++++++++--------------
>  1 file changed, 66 insertions(+), 39 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 942adf0..e1921fe7 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1762,49 +1762,76 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  		dev_priv->display.calc_cdclk_state = skl_calc_cdclk_state;
>  	}
>  
> -	if (IS_GEN9_BC(dev_priv))
> -		dev_priv->display.get_cdclk = skl_get_cdclk;
> -	else if (IS_GEN9_LP(dev_priv))
> -		dev_priv->display.get_cdclk = bxt_get_cdclk;
> -	else if (IS_BROADWELL(dev_priv))
> -		dev_priv->display.get_cdclk = bdw_get_cdclk;
> -	else if (IS_HASWELL(dev_priv))
> -		dev_priv->display.get_cdclk = hsw_get_cdclk;
> -	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> -		dev_priv->display.get_cdclk = vlv_get_cdclk;
> -	else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
> +	switch (INTEL_INFO(dev_priv)->platform) {
> +	case INTEL_PLATFORM_UNINITIALIZED:
> +		MISSING_CASE(INTEL_INFO(dev_priv)->platform);
> +		/* Fall through. */
> +	case INTEL_I830:

The diff might come out nicer if you didn't reverse the list. Right now
it's quite hard to read.

> +		dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
> +		break;
> +	case INTEL_I845G:
> +		dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
> +		break;
> +	case INTEL_I85X:
> +		dev_priv->display.get_cdclk = i85x_get_cdclk;
> +		break;
> +	case INTEL_I865G:
> +		dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
> +		break;
> +	case INTEL_I915G:
> +		dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
> +		break;
> +	case INTEL_I915GM:
> +		dev_priv->display.get_cdclk = i915gm_get_cdclk;
> +		break;
> +	case INTEL_I945G:
>  		dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
> -	else if (IS_GEN5(dev_priv))
> -		dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
> -	else if (IS_GM45(dev_priv))
> -		dev_priv->display.get_cdclk = gm45_get_cdclk;
> -	else if (IS_G45(dev_priv))
> +		break;
> +	case INTEL_I945GM:
> +		dev_priv->display.get_cdclk = i945gm_get_cdclk;
> +		break;
> +	case INTEL_G33:
>  		dev_priv->display.get_cdclk = g33_get_cdclk;
> -	else if (IS_I965GM(dev_priv))
> -		dev_priv->display.get_cdclk = i965gm_get_cdclk;
> -	else if (IS_I965G(dev_priv))
> -		dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
> -	else if (IS_PINEVIEW(dev_priv))
> +		break;
> +	case INTEL_PINEVIEW:
>  		dev_priv->display.get_cdclk = pnv_get_cdclk;
> -	else if (IS_G33(dev_priv))
> +		break;
> +	case INTEL_I965G:
> +		dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
> +		break;
> +	case INTEL_I965GM:
> +		dev_priv->display.get_cdclk = i965gm_get_cdclk;
> +		break;
> +	case INTEL_G45:
>  		dev_priv->display.get_cdclk = g33_get_cdclk;
> -	else if (IS_I945GM(dev_priv))
> -		dev_priv->display.get_cdclk = i945gm_get_cdclk;
> -	else if (IS_I945G(dev_priv))
> +		break;
> +	case INTEL_GM45:
> +		dev_priv->display.get_cdclk = gm45_get_cdclk;
> +		break;
> +	case INTEL_IRONLAKE:
> +		dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
> +		break;
> +	case INTEL_SANDYBRIDGE:
> +	case INTEL_IVYBRIDGE:
>  		dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
> -	else if (IS_I915GM(dev_priv))
> -		dev_priv->display.get_cdclk = i915gm_get_cdclk;
> -	else if (IS_I915G(dev_priv))
> -		dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
> -	else if (IS_I865G(dev_priv))
> -		dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
> -	else if (IS_I85X(dev_priv))
> -		dev_priv->display.get_cdclk = i85x_get_cdclk;
> -	else if (IS_I845G(dev_priv))
> -		dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
> -	else { /* 830 */
> -		WARN(!IS_I830(dev_priv),
> -		     "Unknown platform. Assuming 133 MHz CDCLK\n");
> -		dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
> +		break;
> +	case INTEL_VALLEYVIEW:
> +	case INTEL_CHERRYVIEW:
> +		dev_priv->display.get_cdclk = vlv_get_cdclk;
> +		break;
> +	case INTEL_HASWELL:
> +		dev_priv->display.get_cdclk = hsw_get_cdclk;
> +		break;
> +	case INTEL_BROADWELL:
> +		dev_priv->display.get_cdclk = bdw_get_cdclk;
> +		break;
> +	case INTEL_SKYLAKE:
> +	case INTEL_KABYLAKE:
> +		dev_priv->display.get_cdclk = skl_get_cdclk;
> +		break;
> +	case INTEL_BROXTON:
> +	case INTEL_GEMINILAKE:
> +		dev_priv->display.get_cdclk = bxt_get_cdclk;
> +		break;
>  	}
>  }
> -- 
> 2.7.4

-- 
Ville Syrjälä
Intel OTC
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