diff for duplicates of <20170221162744.GA29581@linaro.org>

diff --git a/a/1.txt b/N1/1.txt
index 6b6f3c7..462396d 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,5 +1,5 @@
 On Tue, Feb 21, 2017 at 02:55:02PM +0800, Chunyan Zhang wrote:
-> From: Orson Zhai <orson.zhai@spreadtrum.com>
+> From: Orson Zhai <orson.zhai-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>
 
 Hello Chunyan,
 
@@ -10,8 +10,8 @@ Hello Chunyan,
 > peripherals IP nodes, sc9860.dtsi contains stuff related to ARM core stuff
 > and sp9860g dts is for the board level.
 > 
-> Signed-off-by: Orson Zhai <orson.zhai@spreadtrum.com>
-> Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+> Signed-off-by: Orson Zhai <orson.zhai-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>
+> Signed-off-by: Chunyan Zhang <chunyan.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>
 > ---
 >  arch/arm64/boot/dts/sprd/Makefile         |   3 +-
 >  arch/arm64/boot/dts/sprd/sc9860.dtsi      | 531 ++++++++++++++++++++++++++++++
@@ -87,7 +87,7 @@ Hello Chunyan,
 > +			};
 > +		};
 > +
-> +		CPU0: cpu at 530000 {
+> +		CPU0: cpu@530000 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530000>;
@@ -95,7 +95,7 @@ Hello Chunyan,
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU1: cpu at 530001 {
+> +		CPU1: cpu@530001 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530001>;
@@ -103,7 +103,7 @@ Hello Chunyan,
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU2: cpu at 530002 {
+> +		CPU2: cpu@530002 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530002>;
@@ -111,7 +111,7 @@ Hello Chunyan,
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU3: cpu at 530003 {
+> +		CPU3: cpu@530003 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530003>;
@@ -119,7 +119,7 @@ Hello Chunyan,
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU4: cpu at 530100 {
+> +		CPU4: cpu@530100 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530100>;
@@ -127,7 +127,7 @@ Hello Chunyan,
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU5: cpu at 530101 {
+> +		CPU5: cpu@530101 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530101>;
@@ -135,7 +135,7 @@ Hello Chunyan,
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU6: cpu at 530102 {
+> +		CPU6: cpu@530102 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530102>;
@@ -143,7 +143,7 @@ Hello Chunyan,
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU7: cpu at 530103 {
+> +		CPU7: cpu@530103 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530103>;
@@ -174,7 +174,7 @@ Hello Chunyan,
 > +		};
 > +	};
 > +
-> +	gic: interrupt-controller at 12001000 {
+> +	gic: interrupt-controller@12001000 {
 > +		compatible = "arm,gic-400";
 > +		reg = <0 0x12001000 0 0x1000>,
 > +		      <0 0x12002000 0 0x2000>,
@@ -224,7 +224,7 @@ Hello Chunyan,
 > +	};
 > +
 > +	soc {
-> +		soc_funnel: funnel at 10001000 {
+> +		soc_funnel: funnel@10001000 {
 
 There is no need for a label ("soc_funnel) before the device name if that
 device is not referenced elsewhere in the DTS.  The same comment applies to most
@@ -238,14 +238,14 @@ of the component listed below.
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +
-> +				port at 0 {
+> +				port@0 {
 > +					reg = <0>;
 > +					soc_funnel_out_port: endpoint {
 > +						remote-endpoint = <&etb_in>;
 > +					};
 > +				};
 > +
-> +				port at 1 {
+> +				port@1 {
 > +					reg = <0>;
 > +					soc_funnel_in_port: endpoint {
 > +						slave-mode;
@@ -256,7 +256,7 @@ of the component listed below.
 > +			};
 > +		};
 > +
-> +		etb at 10003000 {
+> +		etb@10003000 {
 > +			compatible = "arm,coresight-tmc", "arm,primecell";
 > +			reg = <0 0x10003000 0 0x1000>;
 > +			clocks = <&ext_26m>;
@@ -270,7 +270,7 @@ of the component listed below.
 > +			};
 > +		};
 > +
-> +		cluster0_funnel: funnel at 11001000 {
+> +		cluster0_funnel: funnel@11001000 {
 > +			compatible = "arm,coresight-funnel", "arm,primecell";
 > +			reg = <0 0x11001000 0 0x1000>;
 > +			clocks = <&ext_26m>;
@@ -279,7 +279,7 @@ of the component listed below.
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +
-> +				port at 0 {
+> +				port@0 {
 > +					reg = <0>;
 > +					cluster0_funnel_out_port: endpoint {
 > +						remote-endpoint =
@@ -287,7 +287,7 @@ of the component listed below.
 > +					};
 > +				};
 > +
-> +				port at 1 {
+> +				port@1 {
 > +					reg = <0>;
 > +					cluster0_funnel_in_port0: endpoint {
 > +						slave-mode;
@@ -295,7 +295,7 @@ of the component listed below.
 > +					};
 > +				};
 > +
-> +				port at 2 {
+> +				port@2 {
 > +					reg = <1>;
 > +					cluster0_funnel_in_port1: endpoint {
 > +						slave-mode;
@@ -303,7 +303,7 @@ of the component listed below.
 > +					};
 > +				};
 > +
-> +				port at 3 {
+> +				port@3 {
 > +					reg = <2>;
 > +					cluster0_funnel_in_port2: endpoint {
 > +						slave-mode;
@@ -311,7 +311,7 @@ of the component listed below.
 > +					};
 > +				};
 > +
-> +				port at 4 {
+> +				port@4 {
 > +					reg = <4>;
 > +					cluster0_funnel_in_port3: endpoint {
 > +						slave-mode;
@@ -321,7 +321,7 @@ of the component listed below.
 > +			};
 > +		};
 > +
-> +		cluster1_funnel: funnel at 11002000 {
+> +		cluster1_funnel: funnel@11002000 {
 > +			compatible = "arm,coresight-funnel", "arm,primecell";
 > +			reg = <0 0x11002000 0 0x1000>;
 > +			clocks = <&ext_26m>;
@@ -330,7 +330,7 @@ of the component listed below.
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +
-> +				port at 0 {
+> +				port@0 {
 > +					reg = <0>;
 > +					cluster1_funnel_out_port: endpoint {
 > +						remote-endpoint =
@@ -338,7 +338,7 @@ of the component listed below.
 > +					};
 > +				};
 > +
-> +				port at 1 {
+> +				port@1 {
 > +					reg = <0>;
 > +					cluster1_funnel_in_port0: endpoint {
 > +						slave-mode;
@@ -346,7 +346,7 @@ of the component listed below.
 > +					};
 > +				};
 > +
-> +				port at 2 {
+> +				port@2 {
 > +					reg = <1>;
 > +					cluster1_funnel_in_port1: endpoint {
 > +						slave-mode;
@@ -354,7 +354,7 @@ of the component listed below.
 > +					};
 > +				};
 > +
-> +				port at 3 {
+> +				port@3 {
 > +					reg = <2>;
 > +					cluster1_funnel_in_port2: endpoint {
 > +						slave-mode;
@@ -362,7 +362,7 @@ of the component listed below.
 > +					};
 > +				};
 > +
-> +				port at 4 {
+> +				port@4 {
 > +					reg = <3>;
 > +					cluster1_funnel_in_port3: endpoint {
 > +						slave-mode;
@@ -372,20 +372,20 @@ of the component listed below.
 > +			};
 > +		};
 > +
-> +		cluster0_etf: etf at 11003000 {
+> +		cluster0_etf: etf@11003000 {
 > +			compatible = "arm,coresight-tmc", "arm,primecell";
 > +			reg = <0 0x11003000 0 0x1000>;
 > +			clocks = <&ext_26m>;
 > +			clock-names = "apb_pclk";
 > +
-> +			port at 0 {
+> +			port@0 {
 > +				cluster0_etf_out: endpoint {
 > +					remote-endpoint =
 > +						<&main_funnel_in_port0>;
 > +				};
 > +			};
 > +
-> +			port at 1 {
+> +			port@1 {
 > +				cluster0_etf_in: endpoint {
 > +					slave-mode;
 > +					remote-endpoint =
@@ -394,20 +394,20 @@ of the component listed below.
 > +			};
 > +		};
 > +
-> +		cluster1_etf: etf at 11004000 {
+> +		cluster1_etf: etf@11004000 {
 > +			compatible = "arm,coresight-tmc", "arm,primecell";
 > +			reg = <0 0x11004000 0 0x1000>;
 > +			clocks = <&ext_26m>;
 > +			clock-names = "apb_pclk";
 > +
-> +			port at 0 {
+> +			port@0 {
 > +				cluster1_etf_out: endpoint {
 > +					remote-endpoint =
 > +						<&main_funnel_in_port1>;
 > +				};
 > +			};
 > +
-> +			port at 1 {
+> +			port@1 {
 > +				cluster1_etf_in: endpoint {
 > +					slave-mode;
 > +					remote-endpoint =
@@ -419,16 +419,16 @@ of the component listed below.
 When more than one port is present it is customary to add another level of
 imbrication like it is done for funnels above:
                          "ports {"
-                                port at 0 {
+                                port@0 {
                                 ...
-                                port at 1 {
+                                port@1 {
                                 ...
                         }
 
 The same comment applies to both etf. 
 
 > +
-> +		main_funnel: funnel at 11005000 {
+> +		main_funnel: funnel@11005000 {
 > +			compatible = "arm,coresight-funnel", "arm,primecell";
 > +			reg = <0 0x11005000 0 0x1000>;
 > +			clocks = <&ext_26m>;
@@ -438,7 +438,7 @@ The same comment applies to both etf.
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +
-> +				port at 0 {
+> +				port@0 {
 > +					reg = <0>;
 > +					main_funnel_out_port: endpoint {
 > +						remote-endpoint =
@@ -446,7 +446,7 @@ The same comment applies to both etf.
 > +					};
 > +				};
 > +
-> +				port at 1 {
+> +				port@1 {
 > +					reg = <0>;
 > +					main_funnel_in_port0: endpoint {
 > +						slave-mode;
@@ -455,7 +455,7 @@ The same comment applies to both etf.
 > +					};
 > +				};
 > +
-> +				port at 2 {
+> +				port@2 {
 > +					reg = <1>;
 > +					main_funnel_in_port1: endpoint {
 > +						slave-mode;
@@ -466,7 +466,7 @@ The same comment applies to both etf.
 > +			};
 > +		};
 > +
-> +		etm at 11440000 {
+> +		etm@11440000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11440000 0 0x1000>;
 > +			cpu = <&CPU0>;
@@ -481,7 +481,7 @@ The same comment applies to both etf.
 > +			};
 > +		};
 > +
-> +		etm at 11540000 {
+> +		etm@11540000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11540000 0 0x1000>;
 > +			cpu = <&CPU1>;
@@ -496,7 +496,7 @@ The same comment applies to both etf.
 > +			};
 > +		};
 > +
-> +		etm at 11640000 {
+> +		etm@11640000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11640000 0 0x1000>;
 > +			cpu = <&CPU2>;
@@ -511,7 +511,7 @@ The same comment applies to both etf.
 > +			};
 > +		};
 > +
-> +		etm at 11740000 {
+> +		etm@11740000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11740000 0 0x1000>;
 > +			cpu = <&CPU3>;
@@ -526,7 +526,7 @@ The same comment applies to both etf.
 > +			};
 > +		};
 > +
-> +		etm at 11840000 {
+> +		etm@11840000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11840000 0 0x1000>;
 > +			cpu = <&CPU4>;
@@ -541,7 +541,7 @@ The same comment applies to both etf.
 > +			};
 > +		};
 > +
-> +		etm at 11940000 {
+> +		etm@11940000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11940000 0 0x1000>;
 > +			cpu = <&CPU5>;
@@ -556,7 +556,7 @@ The same comment applies to both etf.
 > +			};
 > +		};
 > +
-> +		etm at 11a40000 {
+> +		etm@11a40000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11a40000 0 0x1000>;
 > +			cpu = <&CPU6>;
@@ -571,7 +571,7 @@ The same comment applies to both etf.
 > +			};
 > +		};
 > +
-> +		etm at 11b40000 {
+> +		etm@11b40000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11b40000 0 0x1000>;
 > +			cpu = <&CPU7>;
@@ -680,7 +680,7 @@ The same comment applies to both etf.
 > +			#size-cells = <1>;
 > +			ranges = <0 0x0 0x70000000 0x10000000>;
 > +
-> +			uart0: serial at 70000000 {
+> +			uart0: serial@70000000 {
 > +				compatible = "sprd,sc9838-uart",
 > +					     "sprd,sc9836-uart";
 > +				reg = <0x000000 0x100>;
@@ -689,7 +689,7 @@ The same comment applies to both etf.
 > +				status = "disabled";
 > +			};
 > +
-> +			uart1: serial at 70100000 {
+> +			uart1: serial@70100000 {
 > +				compatible = "sprd,sc9838-uart",
 > +					     "sprd,sc9836-uart";
 > +				reg = <0x100000 0x100>;
@@ -698,7 +698,7 @@ The same comment applies to both etf.
 > +				status = "disabled";
 > +			};
 > +
-> +			uart2: serial at 70200000 {
+> +			uart2: serial@70200000 {
 > +				compatible = "sprd,sc9838-uart",
 > +					     "sprd,sc9836-uart";
 > +				reg = <0x200000 0x100>;
@@ -707,7 +707,7 @@ The same comment applies to both etf.
 > +				status = "disabled";
 > +			};
 > +
-> +			uart3: serial at 70300000 {
+> +			uart3: serial@70300000 {
 > +				compatible = "sprd,sc9838-uart",
 > +					     "sprd,sc9836-uart";
 > +				reg = <0x300000 0x100>;
@@ -731,5 +731,9 @@ The same comment applies to both etf.
 > 
 > _______________________________________________
 > linux-arm-kernel mailing list
-> linux-arm-kernel at lists.infradead.org
+> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
 > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
+--
+To unsubscribe from this list: send the line "unsubscribe devicetree" in
+the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
+More majordomo info at  http://vger.kernel.org/majordomo-info.html
diff --git a/a/content_digest b/N1/content_digest
index 93fd0c0..539f154 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,13 +1,26 @@
  "ref\01487660104-15693-1-git-send-email-chunyan.zhang@spreadtrum.com\0"
  "ref\01487660104-15693-2-git-send-email-chunyan.zhang@spreadtrum.com\0"
- "From\0mathieu.poirier@linaro.org (Mathieu Poirier)\0"
- "Subject\0[PATCH V2 1/3] arm64: dts: Add basic DT to support Spreadtrum's SP9860G\0"
+ "ref\01487660104-15693-2-git-send-email-chunyan.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org\0"
+ "From\0Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0"
+ "Subject\0Re: [PATCH V2 1/3] arm64: dts: Add basic DT to support Spreadtrum's SP9860G\0"
  "Date\0Tue, 21 Feb 2017 09:27:44 -0700\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
+ "To\0Chunyan Zhang <chunyan.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>\0"
+ "Cc\0robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org"
+  mark.rutland-5wv7dgnIgG8@public.gmane.org
+  gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org
+  catalin.marinas-5wv7dgnIgG8@public.gmane.org
+  will.deacon-5wv7dgnIgG8@public.gmane.org
+  arnd-r2nGTMty4D4@public.gmane.org
+  devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
+  orson.zhai-lxIno14LUO0EEoCn2XhGlw@public.gmane.org
+  zhang.lyra-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
+  linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
+  sudeep.holla-5wv7dgnIgG8@public.gmane.org
+ " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0"
  "\00:1\0"
  "b\0"
  "On Tue, Feb 21, 2017 at 02:55:02PM +0800, Chunyan Zhang wrote:\n"
- "> From: Orson Zhai <orson.zhai@spreadtrum.com>\n"
+ "> From: Orson Zhai <orson.zhai-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>\n"
  "\n"
  "Hello Chunyan,\n"
  "\n"
@@ -18,8 +31,8 @@
  "> peripherals IP nodes, sc9860.dtsi contains stuff related to ARM core stuff\n"
  "> and sp9860g dts is for the board level.\n"
  "> \n"
- "> Signed-off-by: Orson Zhai <orson.zhai@spreadtrum.com>\n"
- "> Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>\n"
+ "> Signed-off-by: Orson Zhai <orson.zhai-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>\n"
+ "> Signed-off-by: Chunyan Zhang <chunyan.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>\n"
  "> ---\n"
  ">  arch/arm64/boot/dts/sprd/Makefile         |   3 +-\n"
  ">  arch/arm64/boot/dts/sprd/sc9860.dtsi      | 531 ++++++++++++++++++++++++++++++\n"
@@ -95,7 +108,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU0: cpu at 530000 {\n"
+ "> +\t\tCPU0: cpu@530000 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530000>;\n"
@@ -103,7 +116,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU1: cpu at 530001 {\n"
+ "> +\t\tCPU1: cpu@530001 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530001>;\n"
@@ -111,7 +124,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU2: cpu at 530002 {\n"
+ "> +\t\tCPU2: cpu@530002 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530002>;\n"
@@ -119,7 +132,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU3: cpu at 530003 {\n"
+ "> +\t\tCPU3: cpu@530003 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530003>;\n"
@@ -127,7 +140,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU4: cpu at 530100 {\n"
+ "> +\t\tCPU4: cpu@530100 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530100>;\n"
@@ -135,7 +148,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU5: cpu at 530101 {\n"
+ "> +\t\tCPU5: cpu@530101 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530101>;\n"
@@ -143,7 +156,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU6: cpu at 530102 {\n"
+ "> +\t\tCPU6: cpu@530102 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530102>;\n"
@@ -151,7 +164,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU7: cpu at 530103 {\n"
+ "> +\t\tCPU7: cpu@530103 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530103>;\n"
@@ -182,7 +195,7 @@
  "> +\t\t};\n"
  "> +\t};\n"
  "> +\n"
- "> +\tgic: interrupt-controller at 12001000 {\n"
+ "> +\tgic: interrupt-controller@12001000 {\n"
  "> +\t\tcompatible = \"arm,gic-400\";\n"
  "> +\t\treg = <0 0x12001000 0 0x1000>,\n"
  "> +\t\t      <0 0x12002000 0 0x2000>,\n"
@@ -232,7 +245,7 @@
  "> +\t};\n"
  "> +\n"
  "> +\tsoc {\n"
- "> +\t\tsoc_funnel: funnel at 10001000 {\n"
+ "> +\t\tsoc_funnel: funnel@10001000 {\n"
  "\n"
  "There is no need for a label (\"soc_funnel) before the device name if that\n"
  "device is not referenced elsewhere in the DTS.  The same comment applies to most\n"
@@ -246,14 +259,14 @@
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\t\t\tport at 0 {\n"
+ "> +\t\t\t\tport@0 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tsoc_funnel_out_port: endpoint {\n"
  "> +\t\t\t\t\t\tremote-endpoint = <&etb_in>;\n"
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 1 {\n"
+ "> +\t\t\t\tport@1 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tsoc_funnel_in_port: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -264,7 +277,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetb at 10003000 {\n"
+ "> +\t\tetb@10003000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-tmc\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x10003000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
@@ -278,7 +291,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tcluster0_funnel: funnel at 11001000 {\n"
+ "> +\t\tcluster0_funnel: funnel@11001000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-funnel\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11001000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
@@ -287,7 +300,7 @@
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\t\t\tport at 0 {\n"
+ "> +\t\t\t\tport@0 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster0_funnel_out_port: endpoint {\n"
  "> +\t\t\t\t\t\tremote-endpoint =\n"
@@ -295,7 +308,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 1 {\n"
+ "> +\t\t\t\tport@1 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster0_funnel_in_port0: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -303,7 +316,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 2 {\n"
+ "> +\t\t\t\tport@2 {\n"
  "> +\t\t\t\t\treg = <1>;\n"
  "> +\t\t\t\t\tcluster0_funnel_in_port1: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -311,7 +324,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 3 {\n"
+ "> +\t\t\t\tport@3 {\n"
  "> +\t\t\t\t\treg = <2>;\n"
  "> +\t\t\t\t\tcluster0_funnel_in_port2: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -319,7 +332,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 4 {\n"
+ "> +\t\t\t\tport@4 {\n"
  "> +\t\t\t\t\treg = <4>;\n"
  "> +\t\t\t\t\tcluster0_funnel_in_port3: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -329,7 +342,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tcluster1_funnel: funnel at 11002000 {\n"
+ "> +\t\tcluster1_funnel: funnel@11002000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-funnel\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11002000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
@@ -338,7 +351,7 @@
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\t\t\tport at 0 {\n"
+ "> +\t\t\t\tport@0 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster1_funnel_out_port: endpoint {\n"
  "> +\t\t\t\t\t\tremote-endpoint =\n"
@@ -346,7 +359,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 1 {\n"
+ "> +\t\t\t\tport@1 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster1_funnel_in_port0: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -354,7 +367,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 2 {\n"
+ "> +\t\t\t\tport@2 {\n"
  "> +\t\t\t\t\treg = <1>;\n"
  "> +\t\t\t\t\tcluster1_funnel_in_port1: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -362,7 +375,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 3 {\n"
+ "> +\t\t\t\tport@3 {\n"
  "> +\t\t\t\t\treg = <2>;\n"
  "> +\t\t\t\t\tcluster1_funnel_in_port2: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -370,7 +383,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 4 {\n"
+ "> +\t\t\t\tport@4 {\n"
  "> +\t\t\t\t\treg = <3>;\n"
  "> +\t\t\t\t\tcluster1_funnel_in_port3: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -380,20 +393,20 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tcluster0_etf: etf at 11003000 {\n"
+ "> +\t\tcluster0_etf: etf@11003000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-tmc\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11003000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
  "> +\t\t\tclock-names = \"apb_pclk\";\n"
  "> +\n"
- "> +\t\t\tport at 0 {\n"
+ "> +\t\t\tport@0 {\n"
  "> +\t\t\t\tcluster0_etf_out: endpoint {\n"
  "> +\t\t\t\t\tremote-endpoint =\n"
  "> +\t\t\t\t\t\t<&main_funnel_in_port0>;\n"
  "> +\t\t\t\t};\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tport at 1 {\n"
+ "> +\t\t\tport@1 {\n"
  "> +\t\t\t\tcluster0_etf_in: endpoint {\n"
  "> +\t\t\t\t\tslave-mode;\n"
  "> +\t\t\t\t\tremote-endpoint =\n"
@@ -402,20 +415,20 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tcluster1_etf: etf at 11004000 {\n"
+ "> +\t\tcluster1_etf: etf@11004000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-tmc\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11004000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
  "> +\t\t\tclock-names = \"apb_pclk\";\n"
  "> +\n"
- "> +\t\t\tport at 0 {\n"
+ "> +\t\t\tport@0 {\n"
  "> +\t\t\t\tcluster1_etf_out: endpoint {\n"
  "> +\t\t\t\t\tremote-endpoint =\n"
  "> +\t\t\t\t\t\t<&main_funnel_in_port1>;\n"
  "> +\t\t\t\t};\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tport at 1 {\n"
+ "> +\t\t\tport@1 {\n"
  "> +\t\t\t\tcluster1_etf_in: endpoint {\n"
  "> +\t\t\t\t\tslave-mode;\n"
  "> +\t\t\t\t\tremote-endpoint =\n"
@@ -427,16 +440,16 @@
  "When more than one port is present it is customary to add another level of\n"
  "imbrication like it is done for funnels above:\n"
  "                         \"ports {\"\n"
- "                                port at 0 {\n"
+ "                                port@0 {\n"
  "                                ...\n"
- "                                port at 1 {\n"
+ "                                port@1 {\n"
  "                                ...\n"
  "                        }\n"
  "\n"
  "The same comment applies to both etf. \n"
  "\n"
  "> +\n"
- "> +\t\tmain_funnel: funnel at 11005000 {\n"
+ "> +\t\tmain_funnel: funnel@11005000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-funnel\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11005000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
@@ -446,7 +459,7 @@
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\t\t\tport at 0 {\n"
+ "> +\t\t\t\tport@0 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tmain_funnel_out_port: endpoint {\n"
  "> +\t\t\t\t\t\tremote-endpoint =\n"
@@ -454,7 +467,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 1 {\n"
+ "> +\t\t\t\tport@1 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tmain_funnel_in_port0: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -463,7 +476,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 2 {\n"
+ "> +\t\t\t\tport@2 {\n"
  "> +\t\t\t\t\treg = <1>;\n"
  "> +\t\t\t\t\tmain_funnel_in_port1: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -474,7 +487,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11440000 {\n"
+ "> +\t\tetm@11440000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11440000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU0>;\n"
@@ -489,7 +502,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11540000 {\n"
+ "> +\t\tetm@11540000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11540000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU1>;\n"
@@ -504,7 +517,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11640000 {\n"
+ "> +\t\tetm@11640000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11640000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU2>;\n"
@@ -519,7 +532,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11740000 {\n"
+ "> +\t\tetm@11740000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11740000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU3>;\n"
@@ -534,7 +547,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11840000 {\n"
+ "> +\t\tetm@11840000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11840000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU4>;\n"
@@ -549,7 +562,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11940000 {\n"
+ "> +\t\tetm@11940000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11940000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU5>;\n"
@@ -564,7 +577,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11a40000 {\n"
+ "> +\t\tetm@11a40000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11a40000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU6>;\n"
@@ -579,7 +592,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11b40000 {\n"
+ "> +\t\tetm@11b40000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11b40000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU7>;\n"
@@ -688,7 +701,7 @@
  "> +\t\t\t#size-cells = <1>;\n"
  "> +\t\t\tranges = <0 0x0 0x70000000 0x10000000>;\n"
  "> +\n"
- "> +\t\t\tuart0: serial at 70000000 {\n"
+ "> +\t\t\tuart0: serial@70000000 {\n"
  "> +\t\t\t\tcompatible = \"sprd,sc9838-uart\",\n"
  "> +\t\t\t\t\t     \"sprd,sc9836-uart\";\n"
  "> +\t\t\t\treg = <0x000000 0x100>;\n"
@@ -697,7 +710,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tuart1: serial at 70100000 {\n"
+ "> +\t\t\tuart1: serial@70100000 {\n"
  "> +\t\t\t\tcompatible = \"sprd,sc9838-uart\",\n"
  "> +\t\t\t\t\t     \"sprd,sc9836-uart\";\n"
  "> +\t\t\t\treg = <0x100000 0x100>;\n"
@@ -706,7 +719,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tuart2: serial at 70200000 {\n"
+ "> +\t\t\tuart2: serial@70200000 {\n"
  "> +\t\t\t\tcompatible = \"sprd,sc9838-uart\",\n"
  "> +\t\t\t\t\t     \"sprd,sc9836-uart\";\n"
  "> +\t\t\t\treg = <0x200000 0x100>;\n"
@@ -715,7 +728,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tuart3: serial at 70300000 {\n"
+ "> +\t\t\tuart3: serial@70300000 {\n"
  "> +\t\t\t\tcompatible = \"sprd,sc9838-uart\",\n"
  "> +\t\t\t\t\t     \"sprd,sc9836-uart\";\n"
  "> +\t\t\t\treg = <0x300000 0x100>;\n"
@@ -739,7 +752,11 @@
  "> \n"
  "> _______________________________________________\n"
  "> linux-arm-kernel mailing list\n"
- "> linux-arm-kernel at lists.infradead.org\n"
- > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
+ "> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\n"
+ "> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel\n"
+ "--\n"
+ "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n"
+ "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n"
+ More majordomo info at  http://vger.kernel.org/majordomo-info.html
 
-12d61537e2bcabb97f883d6d8a3faedb43fea13fac222583c6b10ed19fe1aae5
+beb3da82f89ae2b3c43ee9b61826699c43a67a67f60c32a56fa2c7668e5cee69
