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From: Christoffer Dall <cdall@linaro.org>
To: Raz <raziebe@gmail.com>
Cc: kvmarm@lists.cs.columbia.edu
Subject: Re: A question about TTBRs
Date: Fri, 24 Feb 2017 11:22:40 +0100	[thread overview]
Message-ID: <20170224102240.GG1409@cbox> (raw)
In-Reply-To: <CAPB=Z-omrvPjkjmQWfLNWtA86XJzEM1wCB1Rbc-2dnd0iUtaDA@mail.gmail.com>

On Fri, Feb 24, 2017 at 09:55:09AM +0000, Raz wrote:
> Hello
> I am reading the arm8a book. According to the documentation the output
> address of each level 3 entry in TTBRx_EL1points to an address in the
> physical memory.
> By looking in the mmu tab in the DS5 studio I can see the TTBRs tables.
> 
> What I do not understand is why while I have 2GB of RAM in the FVP (
> /proc/meminfo ) some page entries ( level 3 ) of the ttbr points to memory
> above 4GB; for instance:
> 
> Output address NP:0xF794D000
> 
> Doesn't the physical memory starts at address zero ? if not, where its
> starting point is configured?

It depends on your particular system where RAM starts, and it does not
necessarily start at zero.  You'd have to check the documentation of
your model or hardware or look at the device tree you use, for example.

-Christoffer

  reply	other threads:[~2017-02-24 10:21 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-24  9:55 A question about TTBRs Raz
2017-02-24 10:22 ` Christoffer Dall [this message]
2017-02-24 12:10   ` Mark Rutland

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