diff for duplicates of <20170225102649.GB6537@griffinp-mac> diff --git a/a/1.txt b/N1/1.txt index 9a56ecd..4f093f2 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -6,10 +6,10 @@ On Wed, 22 Feb 2017, Jiancheng Xue wrote: > Hi3798CV200 with an integrated quad-core 64-bit ARM Cortex A53 > processor and high performance Mali T720 GPU. > -> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> -> Reviewed-by: Alex Elder <elder@linaro.org> +> Signed-off-by: Jiancheng Xue <xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> +> Reviewed-by: Alex Elder <elder-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> -Acked-by: Peter Griffin <peter.griffin@linaro.org> +Acked-by: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > --- > Changed Log: @@ -80,7 +80,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + stdout-path = "serial0:115200n8"; > + }; > + -> + memory at 0 { +> + memory@0 { > + device_type = "memory"; > + reg = <0x0 0x0 0x0 0x80000000>; > + }; @@ -207,7 +207,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + phy-mode = "rgmii"; > + hisilicon,phy-reset-delays-us = <10000 10000 30000>; > + -> + eth_phy1: phy at 3 { +> + eth_phy1: phy@3 { > + reg = <3>; > + }; > +}; @@ -259,28 +259,28 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + #address-cells = <2>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + }; > + -> + cpu at 1 { +> + cpu@1 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + }; > + -> + cpu at 2 { +> + cpu@2 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x2>; > + enable-method = "psci"; > + }; > + -> + cpu at 3 { +> + cpu@3 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x3>; @@ -288,7 +288,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + }; > + }; > + -> + gic: interrupt-controller at f1001000 { +> + gic: interrupt-controller@f1001000 { > + compatible = "arm,gic-400"; > + reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ > + <0x0 0xf1002000 0x0 0x100>; /* GICC */ @@ -305,13 +305,13 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; > + }; > + -> + soc: soc at f0000000 { +> + soc: soc@f0000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x0 0xf0000000 0x10000000>; > + -> + crg: clock-reset-controller at 8a22000 { +> + crg: clock-reset-controller@8a22000 { > + compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd"; > + reg = <0x8a22000 0x1000>; > + #clock-cells = <1>; @@ -326,14 +326,14 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + }; > + }; > + -> + sysctrl: system-controller at 8000000 { +> + sysctrl: system-controller@8000000 { > + compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; > + reg = <0x8000000 0x1000>; > + #clock-cells = <1>; > + #reset-cells = <2>; > + }; > + -> + uart0: serial at 8b00000 { +> + uart0: serial@8b00000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x8b00000 0x1000>; > + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; @@ -342,7 +342,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + uart2: serial at 8b02000 { +> + uart2: serial@8b02000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x8b02000 0x1000>; > + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; @@ -351,7 +351,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + i2c0: i2c at 8b10000 { +> + i2c0: i2c@8b10000 { > + compatible = "hisilicon,hix5hd2-i2c"; > + reg = <0x8b10000 0x1000>; > + #address-cells = <1>; @@ -362,7 +362,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + i2c1: i2c at 8b11000 { +> + i2c1: i2c@8b11000 { > + compatible = "hisilicon,hix5hd2-i2c"; > + reg = <0x8b11000 0x1000>; > + #address-cells = <1>; @@ -373,7 +373,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + i2c2: i2c at 8b12000 { +> + i2c2: i2c@8b12000 { > + compatible = "hisilicon,hix5hd2-i2c"; > + reg = <0x8b12000 0x1000>; > + #address-cells = <1>; @@ -384,7 +384,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + i2c3: i2c at 8b13000 { +> + i2c3: i2c@8b13000 { > + compatible = "hisilicon,hix5hd2-i2c"; > + reg = <0x8b13000 0x1000>; > + #address-cells = <1>; @@ -395,7 +395,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + i2c4: i2c at 8b14000 { +> + i2c4: i2c@8b14000 { > + compatible = "hisilicon,hix5hd2-i2c"; > + reg = <0x8b14000 0x1000>; > + #address-cells = <1>; @@ -406,7 +406,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + spi0: spi at 8b1a000 { +> + spi0: spi@8b1a000 { > + compatible = "arm,pl022", "arm,primecell"; > + reg = <0x8b1a000 0x1000>; > + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -419,7 +419,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + emmc: mmc at 9830000 { +> + emmc: mmc@9830000 { > + compatible = "snps,dw-mshc"; > + reg = <0x9830000 0x10000>; > + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; @@ -428,7 +428,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + clock-names = "ciu", "biu"; > + }; > + -> + gpio0: gpio at 8b20000 { +> + gpio0: gpio@8b20000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b20000 0x1000>; > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; @@ -441,7 +441,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio1: gpio at 8b21000 { +> + gpio1: gpio@8b21000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b21000 0x1000>; > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; @@ -454,7 +454,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio2: gpio at 8b22000 { +> + gpio2: gpio@8b22000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b22000 0x1000>; > + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; @@ -467,7 +467,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio3: gpio at 8b23000 { +> + gpio3: gpio@8b23000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b23000 0x1000>; > + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; @@ -480,7 +480,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio4: gpio at 8b24000 { +> + gpio4: gpio@8b24000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b24000 0x1000>; > + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; @@ -493,7 +493,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio5: gpio at 8004000 { +> + gpio5: gpio@8004000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8004000 0x1000>; > + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; @@ -506,7 +506,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio6: gpio at 8b26000 { +> + gpio6: gpio@8b26000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b26000 0x1000>; > + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; @@ -519,7 +519,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio7: gpio at 8b27000 { +> + gpio7: gpio@8b27000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b27000 0x1000>; > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; @@ -532,7 +532,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio8: gpio at 8b28000 { +> + gpio8: gpio@8b28000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b28000 0x1000>; > + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; @@ -545,7 +545,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio9: gpio at 8b29000 { +> + gpio9: gpio@8b29000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b29000 0x1000>; > + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; @@ -558,7 +558,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio10: gpio at 8b2a000 { +> + gpio10: gpio@8b2a000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b2a000 0x1000>; > + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; @@ -571,7 +571,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio11: gpio at 8b2b000 { +> + gpio11: gpio@8b2b000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b2b000 0x1000>; > + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; @@ -584,7 +584,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio12: gpio at 8b2c000 { +> + gpio12: gpio@8b2c000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b2c000 0x1000>; > + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; @@ -597,7 +597,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gmac0: ethernet at 9840000 { +> + gmac0: ethernet@9840000 { > + compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; > + reg = <0x9840000 0x1000>, > + <0x984300c 0x4>; @@ -612,7 +612,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gmac1: ethernet at 9841000 { +> + gmac1: ethernet@9841000 { > + compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; > + reg = <0x9841000 0x1000>, > + <0x9843010 0x4>; @@ -627,7 +627,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + ir: ir at 8001000 { +> + ir: ir@8001000 { > + compatible = "hisilicon,hix5hd2-ir"; > + reg = <0x8001000 0x1000>; > + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; @@ -636,3 +636,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + }; > + }; > +}; +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 771a152..38897d4 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,22 @@ "ref\01487752716-14824-1-git-send-email-xuejiancheng@hisilicon.com\0" "ref\01487752716-14824-3-git-send-email-xuejiancheng@hisilicon.com\0" - "From\0peter.griffin@linaro.org (Peter Griffin)\0" - "Subject\0[PATCH v2 2/2] arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board\0" + "ref\01487752716-14824-3-git-send-email-xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org\0" + "From\0Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" + "Subject\0Re: [PATCH v2 2/2] arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board\0" "Date\0Sat, 25 Feb 2017 10:26:49 +0000\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Jiancheng Xue <xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>\0" + "Cc\0robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" + catalin.marinas-5wv7dgnIgG8@public.gmane.org + will.deacon-5wv7dgnIgG8@public.gmane.org + arnd-r2nGTMty4D4@public.gmane.org + xuwei5-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + elder-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + mark.gregotski-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + hermit.wangheming-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org + " yanhaifeng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org\0" "\00:1\0" "b\0" "On Wed, 22 Feb 2017, Jiancheng Xue wrote:\n" @@ -14,10 +27,10 @@ "> Hi3798CV200 with an integrated quad-core 64-bit ARM Cortex A53\n" "> processor and high performance Mali T720 GPU.\n" "> \n" - "> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>\n" - "> Reviewed-by: Alex Elder <elder@linaro.org>\n" + "> Signed-off-by: Jiancheng Xue <xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>\n" + "> Reviewed-by: Alex Elder <elder-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\n" "\n" - "Acked-by: Peter Griffin <peter.griffin@linaro.org>\n" + "Acked-by: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\n" "\n" "> ---\n" "> Changed Log:\n" @@ -88,7 +101,7 @@ "> +\t\tstdout-path = \"serial0:115200n8\";\n" "> +\t};\n" "> +\n" - "> +\tmemory at 0 {\n" + "> +\tmemory@0 {\n" "> +\t\tdevice_type = \"memory\";\n" "> +\t\treg = <0x0 0x0 0x0 0x80000000>;\n" "> +\t};\n" @@ -215,7 +228,7 @@ "> +\tphy-mode = \"rgmii\";\n" "> +\thisilicon,phy-reset-delays-us = <10000 10000 30000>;\n" "> +\n" - "> +\teth_phy1: phy at 3 {\n" + "> +\teth_phy1: phy@3 {\n" "> +\t\treg = <3>;\n" "> +\t};\n" "> +};\n" @@ -267,28 +280,28 @@ "> +\t\t#address-cells = <2>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x0>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x1>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x2>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x3>;\n" @@ -296,7 +309,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at f1001000 {\n" + "> +\tgic: interrupt-controller@f1001000 {\n" "> +\t\tcompatible = \"arm,gic-400\";\n" "> +\t\treg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */\n" "> +\t\t <0x0 0xf1002000 0x0 0x100>; /* GICC */\n" @@ -313,13 +326,13 @@ "> +\t\t\t <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;\n" "> +\t};\n" "> +\n" - "> +\tsoc: soc at f0000000 {\n" + "> +\tsoc: soc@f0000000 {\n" "> +\t\tcompatible = \"simple-bus\";\n" "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <1>;\n" "> +\t\tranges = <0x0 0x0 0xf0000000 0x10000000>;\n" "> +\n" - "> +\t\tcrg: clock-reset-controller at 8a22000 {\n" + "> +\t\tcrg: clock-reset-controller@8a22000 {\n" "> +\t\t\tcompatible = \"hisilicon,hi3798cv200-crg\", \"syscon\", \"simple-mfd\";\n" "> +\t\t\treg = <0x8a22000 0x1000>;\n" "> +\t\t\t#clock-cells = <1>;\n" @@ -334,14 +347,14 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tsysctrl: system-controller at 8000000 {\n" + "> +\t\tsysctrl: system-controller@8000000 {\n" "> +\t\t\tcompatible = \"hisilicon,hi3798cv200-sysctrl\", \"syscon\";\n" "> +\t\t\treg = <0x8000000 0x1000>;\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\t#reset-cells = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart0: serial at 8b00000 {\n" + "> +\t\tuart0: serial@8b00000 {\n" "> +\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b00000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -350,7 +363,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart2: serial at 8b02000 {\n" + "> +\t\tuart2: serial@8b02000 {\n" "> +\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b02000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -359,7 +372,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c0: i2c at 8b10000 {\n" + "> +\t\ti2c0: i2c@8b10000 {\n" "> +\t\t\tcompatible = \"hisilicon,hix5hd2-i2c\";\n" "> +\t\t\treg = <0x8b10000 0x1000>;\n" "> +\t\t\t#address-cells = <1>;\n" @@ -370,7 +383,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c1: i2c at 8b11000 {\n" + "> +\t\ti2c1: i2c@8b11000 {\n" "> +\t\t\tcompatible = \"hisilicon,hix5hd2-i2c\";\n" "> +\t\t\treg = <0x8b11000 0x1000>;\n" "> +\t\t\t#address-cells = <1>;\n" @@ -381,7 +394,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c2: i2c at 8b12000 {\n" + "> +\t\ti2c2: i2c@8b12000 {\n" "> +\t\t\tcompatible = \"hisilicon,hix5hd2-i2c\";\n" "> +\t\t\treg = <0x8b12000 0x1000>;\n" "> +\t\t\t#address-cells = <1>;\n" @@ -392,7 +405,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c3: i2c at 8b13000 {\n" + "> +\t\ti2c3: i2c@8b13000 {\n" "> +\t\t\tcompatible = \"hisilicon,hix5hd2-i2c\";\n" "> +\t\t\treg = <0x8b13000 0x1000>;\n" "> +\t\t\t#address-cells = <1>;\n" @@ -403,7 +416,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c4: i2c at 8b14000 {\n" + "> +\t\ti2c4: i2c@8b14000 {\n" "> +\t\t\tcompatible = \"hisilicon,hix5hd2-i2c\";\n" "> +\t\t\treg = <0x8b14000 0x1000>;\n" "> +\t\t\t#address-cells = <1>;\n" @@ -414,7 +427,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tspi0: spi at 8b1a000 {\n" + "> +\t\tspi0: spi@8b1a000 {\n" "> +\t\t\tcompatible = \"arm,pl022\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b1a000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -427,7 +440,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\temmc: mmc at 9830000 {\n" + "> +\t\temmc: mmc@9830000 {\n" "> +\t\t\tcompatible = \"snps,dw-mshc\";\n" "> +\t\t\treg = <0x9830000 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -436,7 +449,7 @@ "> +\t\t\tclock-names = \"ciu\", \"biu\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio0: gpio at 8b20000 {\n" + "> +\t\tgpio0: gpio@8b20000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b20000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -449,7 +462,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio1: gpio at 8b21000 {\n" + "> +\t\tgpio1: gpio@8b21000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b21000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -462,7 +475,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio2: gpio at 8b22000 {\n" + "> +\t\tgpio2: gpio@8b22000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b22000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -475,7 +488,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio3: gpio at 8b23000 {\n" + "> +\t\tgpio3: gpio@8b23000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b23000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -488,7 +501,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio4: gpio at 8b24000 {\n" + "> +\t\tgpio4: gpio@8b24000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b24000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -501,7 +514,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio5: gpio at 8004000 {\n" + "> +\t\tgpio5: gpio@8004000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8004000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -514,7 +527,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio6: gpio at 8b26000 {\n" + "> +\t\tgpio6: gpio@8b26000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b26000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -527,7 +540,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio7: gpio at 8b27000 {\n" + "> +\t\tgpio7: gpio@8b27000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b27000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -540,7 +553,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio8: gpio at 8b28000 {\n" + "> +\t\tgpio8: gpio@8b28000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b28000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -553,7 +566,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio9: gpio at 8b29000 {\n" + "> +\t\tgpio9: gpio@8b29000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b29000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -566,7 +579,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio10: gpio at 8b2a000 {\n" + "> +\t\tgpio10: gpio@8b2a000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b2a000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -579,7 +592,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio11: gpio at 8b2b000 {\n" + "> +\t\tgpio11: gpio@8b2b000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b2b000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -592,7 +605,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio12: gpio at 8b2c000 {\n" + "> +\t\tgpio12: gpio@8b2c000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b2c000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -605,7 +618,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgmac0: ethernet at 9840000 {\n" + "> +\t\tgmac0: ethernet@9840000 {\n" "> +\t\t\tcompatible = \"hisilicon,hi3798cv200-gmac\", \"hisilicon,hisi-gmac-v2\";\n" "> +\t\t\treg = <0x9840000 0x1000>,\n" "> +\t\t\t <0x984300c 0x4>;\n" @@ -620,7 +633,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgmac1: ethernet at 9841000 {\n" + "> +\t\tgmac1: ethernet@9841000 {\n" "> +\t\t\tcompatible = \"hisilicon,hi3798cv200-gmac\", \"hisilicon,hisi-gmac-v2\";\n" "> +\t\t\treg = <0x9841000 0x1000>,\n" "> +\t\t\t <0x9843010 0x4>;\n" @@ -635,7 +648,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tir: ir at 8001000 {\n" + "> +\t\tir: ir@8001000 {\n" "> +\t\t\tcompatible = \"hisilicon,hix5hd2-ir\";\n" "> +\t\t\treg = <0x8001000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -643,6 +656,10 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\t};\n" - > +}; + "> +};\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -843d06dcd50ee25d66b30aea1100b45b214c5e67b4178bfea49093951b8065c6 +ba8357cd92546935b19095575c89ae7d8f43f9bc0d1eb3b958a856b44a1128c4
diff --git a/a/1.txt b/N2/1.txt index 9a56ecd..e8aa803 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -80,7 +80,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + stdout-path = "serial0:115200n8"; > + }; > + -> + memory at 0 { +> + memory@0 { > + device_type = "memory"; > + reg = <0x0 0x0 0x0 0x80000000>; > + }; @@ -207,7 +207,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + phy-mode = "rgmii"; > + hisilicon,phy-reset-delays-us = <10000 10000 30000>; > + -> + eth_phy1: phy at 3 { +> + eth_phy1: phy@3 { > + reg = <3>; > + }; > +}; @@ -259,28 +259,28 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + #address-cells = <2>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + }; > + -> + cpu at 1 { +> + cpu@1 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + }; > + -> + cpu at 2 { +> + cpu@2 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x2>; > + enable-method = "psci"; > + }; > + -> + cpu at 3 { +> + cpu@3 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x3>; @@ -288,7 +288,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + }; > + }; > + -> + gic: interrupt-controller at f1001000 { +> + gic: interrupt-controller@f1001000 { > + compatible = "arm,gic-400"; > + reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ > + <0x0 0xf1002000 0x0 0x100>; /* GICC */ @@ -305,13 +305,13 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; > + }; > + -> + soc: soc at f0000000 { +> + soc: soc@f0000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x0 0xf0000000 0x10000000>; > + -> + crg: clock-reset-controller at 8a22000 { +> + crg: clock-reset-controller@8a22000 { > + compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd"; > + reg = <0x8a22000 0x1000>; > + #clock-cells = <1>; @@ -326,14 +326,14 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + }; > + }; > + -> + sysctrl: system-controller at 8000000 { +> + sysctrl: system-controller@8000000 { > + compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; > + reg = <0x8000000 0x1000>; > + #clock-cells = <1>; > + #reset-cells = <2>; > + }; > + -> + uart0: serial at 8b00000 { +> + uart0: serial@8b00000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x8b00000 0x1000>; > + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; @@ -342,7 +342,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + uart2: serial at 8b02000 { +> + uart2: serial@8b02000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x8b02000 0x1000>; > + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; @@ -351,7 +351,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + i2c0: i2c at 8b10000 { +> + i2c0: i2c@8b10000 { > + compatible = "hisilicon,hix5hd2-i2c"; > + reg = <0x8b10000 0x1000>; > + #address-cells = <1>; @@ -362,7 +362,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + i2c1: i2c at 8b11000 { +> + i2c1: i2c@8b11000 { > + compatible = "hisilicon,hix5hd2-i2c"; > + reg = <0x8b11000 0x1000>; > + #address-cells = <1>; @@ -373,7 +373,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + i2c2: i2c at 8b12000 { +> + i2c2: i2c@8b12000 { > + compatible = "hisilicon,hix5hd2-i2c"; > + reg = <0x8b12000 0x1000>; > + #address-cells = <1>; @@ -384,7 +384,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + i2c3: i2c at 8b13000 { +> + i2c3: i2c@8b13000 { > + compatible = "hisilicon,hix5hd2-i2c"; > + reg = <0x8b13000 0x1000>; > + #address-cells = <1>; @@ -395,7 +395,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + i2c4: i2c at 8b14000 { +> + i2c4: i2c@8b14000 { > + compatible = "hisilicon,hix5hd2-i2c"; > + reg = <0x8b14000 0x1000>; > + #address-cells = <1>; @@ -406,7 +406,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + spi0: spi at 8b1a000 { +> + spi0: spi@8b1a000 { > + compatible = "arm,pl022", "arm,primecell"; > + reg = <0x8b1a000 0x1000>; > + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -419,7 +419,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + emmc: mmc at 9830000 { +> + emmc: mmc@9830000 { > + compatible = "snps,dw-mshc"; > + reg = <0x9830000 0x10000>; > + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; @@ -428,7 +428,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + clock-names = "ciu", "biu"; > + }; > + -> + gpio0: gpio at 8b20000 { +> + gpio0: gpio@8b20000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b20000 0x1000>; > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; @@ -441,7 +441,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio1: gpio at 8b21000 { +> + gpio1: gpio@8b21000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b21000 0x1000>; > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; @@ -454,7 +454,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio2: gpio at 8b22000 { +> + gpio2: gpio@8b22000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b22000 0x1000>; > + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; @@ -467,7 +467,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio3: gpio at 8b23000 { +> + gpio3: gpio@8b23000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b23000 0x1000>; > + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; @@ -480,7 +480,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio4: gpio at 8b24000 { +> + gpio4: gpio@8b24000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b24000 0x1000>; > + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; @@ -493,7 +493,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio5: gpio at 8004000 { +> + gpio5: gpio@8004000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8004000 0x1000>; > + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; @@ -506,7 +506,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio6: gpio at 8b26000 { +> + gpio6: gpio@8b26000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b26000 0x1000>; > + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; @@ -519,7 +519,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio7: gpio at 8b27000 { +> + gpio7: gpio@8b27000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b27000 0x1000>; > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; @@ -532,7 +532,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio8: gpio at 8b28000 { +> + gpio8: gpio@8b28000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b28000 0x1000>; > + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; @@ -545,7 +545,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio9: gpio at 8b29000 { +> + gpio9: gpio@8b29000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b29000 0x1000>; > + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; @@ -558,7 +558,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio10: gpio at 8b2a000 { +> + gpio10: gpio@8b2a000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b2a000 0x1000>; > + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; @@ -571,7 +571,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio11: gpio at 8b2b000 { +> + gpio11: gpio@8b2b000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b2b000 0x1000>; > + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; @@ -584,7 +584,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gpio12: gpio at 8b2c000 { +> + gpio12: gpio@8b2c000 { > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0x8b2c000 0x1000>; > + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; @@ -597,7 +597,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gmac0: ethernet at 9840000 { +> + gmac0: ethernet@9840000 { > + compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; > + reg = <0x9840000 0x1000>, > + <0x984300c 0x4>; @@ -612,7 +612,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + gmac1: ethernet at 9841000 { +> + gmac1: ethernet@9841000 { > + compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; > + reg = <0x9841000 0x1000>, > + <0x9843010 0x4>; @@ -627,7 +627,7 @@ Acked-by: Peter Griffin <peter.griffin@linaro.org> > + status = "disabled"; > + }; > + -> + ir: ir at 8001000 { +> + ir: ir@8001000 { > + compatible = "hisilicon,hix5hd2-ir"; > + reg = <0x8001000 0x1000>; > + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; diff --git a/a/content_digest b/N2/content_digest index 771a152..8edae66 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,9 +1,21 @@ "ref\01487752716-14824-1-git-send-email-xuejiancheng@hisilicon.com\0" "ref\01487752716-14824-3-git-send-email-xuejiancheng@hisilicon.com\0" - "From\0peter.griffin@linaro.org (Peter Griffin)\0" - "Subject\0[PATCH v2 2/2] arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board\0" + "From\0Peter Griffin <peter.griffin@linaro.org>\0" + "Subject\0Re: [PATCH v2 2/2] arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board\0" "Date\0Sat, 25 Feb 2017 10:26:49 +0000\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Jiancheng Xue <xuejiancheng@hisilicon.com>\0" + "Cc\0robh+dt@kernel.org" + catalin.marinas@arm.com + will.deacon@arm.com + arnd@arndb.de + xuwei5@hisilicon.com + devicetree@vger.kernel.org + linux-kernel@vger.kernel.org + linux-arm-kernel@lists.infradead.org + elder@linaro.org + mark.gregotski@linaro.org + hermit.wangheming@hisilicon.com + " yanhaifeng@hisilicon.com\0" "\00:1\0" "b\0" "On Wed, 22 Feb 2017, Jiancheng Xue wrote:\n" @@ -88,7 +100,7 @@ "> +\t\tstdout-path = \"serial0:115200n8\";\n" "> +\t};\n" "> +\n" - "> +\tmemory at 0 {\n" + "> +\tmemory@0 {\n" "> +\t\tdevice_type = \"memory\";\n" "> +\t\treg = <0x0 0x0 0x0 0x80000000>;\n" "> +\t};\n" @@ -215,7 +227,7 @@ "> +\tphy-mode = \"rgmii\";\n" "> +\thisilicon,phy-reset-delays-us = <10000 10000 30000>;\n" "> +\n" - "> +\teth_phy1: phy at 3 {\n" + "> +\teth_phy1: phy@3 {\n" "> +\t\treg = <3>;\n" "> +\t};\n" "> +};\n" @@ -267,28 +279,28 @@ "> +\t\t#address-cells = <2>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x0>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x1>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x2>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x3>;\n" @@ -296,7 +308,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at f1001000 {\n" + "> +\tgic: interrupt-controller@f1001000 {\n" "> +\t\tcompatible = \"arm,gic-400\";\n" "> +\t\treg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */\n" "> +\t\t <0x0 0xf1002000 0x0 0x100>; /* GICC */\n" @@ -313,13 +325,13 @@ "> +\t\t\t <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;\n" "> +\t};\n" "> +\n" - "> +\tsoc: soc at f0000000 {\n" + "> +\tsoc: soc@f0000000 {\n" "> +\t\tcompatible = \"simple-bus\";\n" "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <1>;\n" "> +\t\tranges = <0x0 0x0 0xf0000000 0x10000000>;\n" "> +\n" - "> +\t\tcrg: clock-reset-controller at 8a22000 {\n" + "> +\t\tcrg: clock-reset-controller@8a22000 {\n" "> +\t\t\tcompatible = \"hisilicon,hi3798cv200-crg\", \"syscon\", \"simple-mfd\";\n" "> +\t\t\treg = <0x8a22000 0x1000>;\n" "> +\t\t\t#clock-cells = <1>;\n" @@ -334,14 +346,14 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tsysctrl: system-controller at 8000000 {\n" + "> +\t\tsysctrl: system-controller@8000000 {\n" "> +\t\t\tcompatible = \"hisilicon,hi3798cv200-sysctrl\", \"syscon\";\n" "> +\t\t\treg = <0x8000000 0x1000>;\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\t#reset-cells = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart0: serial at 8b00000 {\n" + "> +\t\tuart0: serial@8b00000 {\n" "> +\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b00000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -350,7 +362,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart2: serial at 8b02000 {\n" + "> +\t\tuart2: serial@8b02000 {\n" "> +\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b02000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -359,7 +371,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c0: i2c at 8b10000 {\n" + "> +\t\ti2c0: i2c@8b10000 {\n" "> +\t\t\tcompatible = \"hisilicon,hix5hd2-i2c\";\n" "> +\t\t\treg = <0x8b10000 0x1000>;\n" "> +\t\t\t#address-cells = <1>;\n" @@ -370,7 +382,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c1: i2c at 8b11000 {\n" + "> +\t\ti2c1: i2c@8b11000 {\n" "> +\t\t\tcompatible = \"hisilicon,hix5hd2-i2c\";\n" "> +\t\t\treg = <0x8b11000 0x1000>;\n" "> +\t\t\t#address-cells = <1>;\n" @@ -381,7 +393,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c2: i2c at 8b12000 {\n" + "> +\t\ti2c2: i2c@8b12000 {\n" "> +\t\t\tcompatible = \"hisilicon,hix5hd2-i2c\";\n" "> +\t\t\treg = <0x8b12000 0x1000>;\n" "> +\t\t\t#address-cells = <1>;\n" @@ -392,7 +404,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c3: i2c at 8b13000 {\n" + "> +\t\ti2c3: i2c@8b13000 {\n" "> +\t\t\tcompatible = \"hisilicon,hix5hd2-i2c\";\n" "> +\t\t\treg = <0x8b13000 0x1000>;\n" "> +\t\t\t#address-cells = <1>;\n" @@ -403,7 +415,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c4: i2c at 8b14000 {\n" + "> +\t\ti2c4: i2c@8b14000 {\n" "> +\t\t\tcompatible = \"hisilicon,hix5hd2-i2c\";\n" "> +\t\t\treg = <0x8b14000 0x1000>;\n" "> +\t\t\t#address-cells = <1>;\n" @@ -414,7 +426,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tspi0: spi at 8b1a000 {\n" + "> +\t\tspi0: spi@8b1a000 {\n" "> +\t\t\tcompatible = \"arm,pl022\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b1a000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -427,7 +439,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\temmc: mmc at 9830000 {\n" + "> +\t\temmc: mmc@9830000 {\n" "> +\t\t\tcompatible = \"snps,dw-mshc\";\n" "> +\t\t\treg = <0x9830000 0x10000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -436,7 +448,7 @@ "> +\t\t\tclock-names = \"ciu\", \"biu\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio0: gpio at 8b20000 {\n" + "> +\t\tgpio0: gpio@8b20000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b20000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -449,7 +461,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio1: gpio at 8b21000 {\n" + "> +\t\tgpio1: gpio@8b21000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b21000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -462,7 +474,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio2: gpio at 8b22000 {\n" + "> +\t\tgpio2: gpio@8b22000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b22000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -475,7 +487,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio3: gpio at 8b23000 {\n" + "> +\t\tgpio3: gpio@8b23000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b23000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -488,7 +500,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio4: gpio at 8b24000 {\n" + "> +\t\tgpio4: gpio@8b24000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b24000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -501,7 +513,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio5: gpio at 8004000 {\n" + "> +\t\tgpio5: gpio@8004000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8004000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -514,7 +526,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio6: gpio at 8b26000 {\n" + "> +\t\tgpio6: gpio@8b26000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b26000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -527,7 +539,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio7: gpio at 8b27000 {\n" + "> +\t\tgpio7: gpio@8b27000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b27000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -540,7 +552,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio8: gpio at 8b28000 {\n" + "> +\t\tgpio8: gpio@8b28000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b28000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -553,7 +565,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio9: gpio at 8b29000 {\n" + "> +\t\tgpio9: gpio@8b29000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b29000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -566,7 +578,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio10: gpio at 8b2a000 {\n" + "> +\t\tgpio10: gpio@8b2a000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b2a000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -579,7 +591,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio11: gpio at 8b2b000 {\n" + "> +\t\tgpio11: gpio@8b2b000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b2b000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -592,7 +604,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio12: gpio at 8b2c000 {\n" + "> +\t\tgpio12: gpio@8b2c000 {\n" "> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n" "> +\t\t\treg = <0x8b2c000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -605,7 +617,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgmac0: ethernet at 9840000 {\n" + "> +\t\tgmac0: ethernet@9840000 {\n" "> +\t\t\tcompatible = \"hisilicon,hi3798cv200-gmac\", \"hisilicon,hisi-gmac-v2\";\n" "> +\t\t\treg = <0x9840000 0x1000>,\n" "> +\t\t\t <0x984300c 0x4>;\n" @@ -620,7 +632,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgmac1: ethernet at 9841000 {\n" + "> +\t\tgmac1: ethernet@9841000 {\n" "> +\t\t\tcompatible = \"hisilicon,hi3798cv200-gmac\", \"hisilicon,hisi-gmac-v2\";\n" "> +\t\t\treg = <0x9841000 0x1000>,\n" "> +\t\t\t <0x9843010 0x4>;\n" @@ -635,7 +647,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tir: ir at 8001000 {\n" + "> +\t\tir: ir@8001000 {\n" "> +\t\t\tcompatible = \"hisilicon,hix5hd2-ir\";\n" "> +\t\t\treg = <0x8001000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -645,4 +657,4 @@ "> +\t};\n" > +}; -843d06dcd50ee25d66b30aea1100b45b214c5e67b4178bfea49093951b8065c6 +68adedc203747d846467f9e19f54306f59551e0f65525748bc4419c666f005ad
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