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diff for duplicates of <20170302162222.GA32058@linaro.org>

diff --git a/a/1.txt b/N1/1.txt
index 1734f94..e0eb4c5 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -84,7 +84,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		CPU0: cpu at 530000 {
+> +		CPU0: cpu@530000 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530000>;
@@ -92,7 +92,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU1: cpu at 530001 {
+> +		CPU1: cpu@530001 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530001>;
@@ -100,7 +100,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU2: cpu at 530002 {
+> +		CPU2: cpu@530002 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530002>;
@@ -108,7 +108,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU3: cpu at 530003 {
+> +		CPU3: cpu@530003 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530003>;
@@ -116,7 +116,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU4: cpu at 530100 {
+> +		CPU4: cpu@530100 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530100>;
@@ -124,7 +124,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU5: cpu at 530101 {
+> +		CPU5: cpu@530101 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530101>;
@@ -132,7 +132,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU6: cpu at 530102 {
+> +		CPU6: cpu@530102 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530102>;
@@ -140,7 +140,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU7: cpu at 530103 {
+> +		CPU7: cpu@530103 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530103>;
@@ -171,7 +171,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +		};
 > +	};
 > +
-> +	gic: interrupt-controller at 12001000 {
+> +	gic: interrupt-controller@12001000 {
 > +		compatible = "arm,gic-400";
 > +		reg = <0 0x12001000 0 0x1000>,
 > +		      <0 0x12002000 0 0x2000>,
@@ -221,7 +221,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +	};
 > +
 > +	soc {
-> +		funnel at 10001000 { /* SoC Funnel */
+> +		funnel@10001000 { /* SoC Funnel */
 > +			compatible = "arm,coresight-funnel", "arm,primecell";
 > +			reg = <0 0x10001000 0 0x1000>;
 > +			clocks = <&ext_26m>;
@@ -230,14 +230,14 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +
-> +				port at 0 {
+> +				port@0 {
 > +					reg = <0>;
 > +					soc_funnel_out_port: endpoint {
 > +						remote-endpoint = <&etb_in>;
 > +					};
 > +				};
 > +
-> +				port at 1 {
+> +				port@1 {
 > +					reg = <0>;
 > +					soc_funnel_in_port: endpoint {
 > +						slave-mode;
@@ -248,7 +248,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etb at 10003000 {
+> +		etb@10003000 {
 > +			compatible = "arm,coresight-tmc", "arm,primecell";
 > +			reg = <0 0x10003000 0 0x1000>;
 > +			clocks = <&ext_26m>;
@@ -262,7 +262,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		funnel at 11001000 { /* Cluster0 Funnel */
+> +		funnel@11001000 { /* Cluster0 Funnel */
 > +			compatible = "arm,coresight-funnel", "arm,primecell";
 > +			reg = <0 0x11001000 0 0x1000>;
 > +			clocks = <&ext_26m>;
@@ -271,7 +271,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +
-> +				port at 0 {
+> +				port@0 {
 > +					reg = <0>;
 > +					cluster0_funnel_out_port: endpoint {
 > +						remote-endpoint =
@@ -279,7 +279,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 1 {
+> +				port@1 {
 > +					reg = <0>;
 > +					cluster0_funnel_in_port0: endpoint {
 > +						slave-mode;
@@ -287,7 +287,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 2 {
+> +				port@2 {
 > +					reg = <1>;
 > +					cluster0_funnel_in_port1: endpoint {
 > +						slave-mode;
@@ -295,7 +295,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 3 {
+> +				port@3 {
 > +					reg = <2>;
 > +					cluster0_funnel_in_port2: endpoint {
 > +						slave-mode;
@@ -303,7 +303,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 4 {
+> +				port@4 {
 > +					reg = <4>;
 > +					cluster0_funnel_in_port3: endpoint {
 > +						slave-mode;
@@ -313,7 +313,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		funnel at 11002000 { /* Cluster1 Funnel */
+> +		funnel@11002000 { /* Cluster1 Funnel */
 > +			compatible = "arm,coresight-funnel", "arm,primecell";
 > +			reg = <0 0x11002000 0 0x1000>;
 > +			clocks = <&ext_26m>;
@@ -322,7 +322,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +
-> +				port at 0 {
+> +				port@0 {
 > +					reg = <0>;
 > +					cluster1_funnel_out_port: endpoint {
 > +						remote-endpoint =
@@ -330,7 +330,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 1 {
+> +				port@1 {
 > +					reg = <0>;
 > +					cluster1_funnel_in_port0: endpoint {
 > +						slave-mode;
@@ -338,7 +338,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 2 {
+> +				port@2 {
 > +					reg = <1>;
 > +					cluster1_funnel_in_port1: endpoint {
 > +						slave-mode;
@@ -346,7 +346,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 3 {
+> +				port@3 {
 > +					reg = <2>;
 > +					cluster1_funnel_in_port2: endpoint {
 > +						slave-mode;
@@ -354,7 +354,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 4 {
+> +				port@4 {
 > +					reg = <3>;
 > +					cluster1_funnel_in_port3: endpoint {
 > +						slave-mode;
@@ -364,7 +364,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etf at 11003000 { /*  ETF on Cluster0 */
+> +		etf@11003000 { /*  ETF on Cluster0 */
 > +			compatible = "arm,coresight-tmc", "arm,primecell";
 > +			reg = <0 0x11003000 0 0x1000>;
 > +			clocks = <&ext_26m>;
@@ -374,7 +374,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +
-> +				port at 0 {
+> +				port@0 {
 > +					reg = <0>;
 > +					cluster0_etf_out: endpoint {
 > +						remote-endpoint =
@@ -382,7 +382,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 1 {
+> +				port@1 {
 > +					reg = <0>;
 > +					cluster0_etf_in: endpoint {
 > +						slave-mode;
@@ -393,7 +393,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etf at 11004000 { /* ETF on Cluster1 */
+> +		etf@11004000 { /* ETF on Cluster1 */
 > +			compatible = "arm,coresight-tmc", "arm,primecell";
 > +			reg = <0 0x11004000 0 0x1000>;
 > +			clocks = <&ext_26m>;
@@ -403,7 +403,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +
-> +				port at 0 {
+> +				port@0 {
 > +					reg = <0>;
 > +					cluster1_etf_out: endpoint {
 > +						remote-endpoint =
@@ -411,7 +411,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 1 {
+> +				port@1 {
 > +					reg = <0>;
 > +					cluster1_etf_in: endpoint {
 > +						slave-mode;
@@ -422,7 +422,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		funnel at 11005000 { /* Main Funnel */
+> +		funnel@11005000 { /* Main Funnel */
 > +			compatible = "arm,coresight-funnel", "arm,primecell";
 > +			reg = <0 0x11005000 0 0x1000>;
 > +			clocks = <&ext_26m>;
@@ -432,7 +432,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +
-> +				port at 0 {
+> +				port@0 {
 > +					reg = <0>;
 > +					main_funnel_out_port: endpoint {
 > +						remote-endpoint =
@@ -440,7 +440,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 1 {
+> +				port@1 {
 > +					reg = <0>;
 > +					main_funnel_in_port0: endpoint {
 > +						slave-mode;
@@ -449,7 +449,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 2 {
+> +				port@2 {
 > +					reg = <1>;
 > +					main_funnel_in_port1: endpoint {
 > +						slave-mode;
@@ -460,7 +460,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etm at 11440000 {
+> +		etm@11440000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11440000 0 0x1000>;
 > +			cpu = <&CPU0>;
@@ -475,7 +475,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etm at 11540000 {
+> +		etm@11540000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11540000 0 0x1000>;
 > +			cpu = <&CPU1>;
@@ -490,7 +490,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etm at 11640000 {
+> +		etm@11640000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11640000 0 0x1000>;
 > +			cpu = <&CPU2>;
@@ -505,7 +505,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etm at 11740000 {
+> +		etm@11740000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11740000 0 0x1000>;
 > +			cpu = <&CPU3>;
@@ -520,7 +520,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etm at 11840000 {
+> +		etm@11840000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11840000 0 0x1000>;
 > +			cpu = <&CPU4>;
@@ -535,7 +535,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etm at 11940000 {
+> +		etm@11940000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11940000 0 0x1000>;
 > +			cpu = <&CPU5>;
@@ -550,7 +550,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etm at 11a40000 {
+> +		etm@11a40000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11a40000 0 0x1000>;
 > +			cpu = <&CPU6>;
@@ -565,7 +565,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etm at 11b40000 {
+> +		etm@11b40000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11b40000 0 0x1000>;
 > +			cpu = <&CPU7>;
@@ -679,7 +679,7 @@ Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
 > +			#size-cells = <1>;
 > +			ranges = <0 0x0 0x70000000 0x10000000>;
 > +
-> +			uart0: serial at 70000000 {
+> +			uart0: serial@70000000 {
 > +				compatible = "sprd,sc9860-uart",
 > +					     "sprd,sc9836-uart";
 > +				reg = <0x000000 0x100>;
@@ -688,7 +688,7 @@ Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
 > +				status = "disabled";
 > +			};
 > +
-> +			uart1: serial at 70100000 {
+> +			uart1: serial@70100000 {
 > +				compatible = "sprd,sc9860-uart",
 > +					     "sprd,sc9836-uart";
 > +				reg = <0x100000 0x100>;
@@ -697,7 +697,7 @@ Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
 > +				status = "disabled";
 > +			};
 > +
-> +			uart2: serial at 70200000 {
+> +			uart2: serial@70200000 {
 > +				compatible = "sprd,sc9860-uart",
 > +					     "sprd,sc9836-uart";
 > +				reg = <0x200000 0x100>;
@@ -706,7 +706,7 @@ Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
 > +				status = "disabled";
 > +			};
 > +
-> +			uart3: serial at 70300000 {
+> +			uart3: serial@70300000 {
 > +				compatible = "sprd,sc9860-uart",
 > +					     "sprd,sc9836-uart";
 > +				reg = <0x300000 0x100>;
@@ -731,5 +731,5 @@ Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
 > 
 > _______________________________________________
 > linux-arm-kernel mailing list
-> linux-arm-kernel at lists.infradead.org
+> linux-arm-kernel@lists.infradead.org
 > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff --git a/a/content_digest b/N1/content_digest
index 4728e2b..dc43363 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,9 +1,21 @@
  "ref\01488435730-6711-1-git-send-email-chunyan.zhang@spreadtrum.com\0"
  "ref\01488435730-6711-2-git-send-email-chunyan.zhang@spreadtrum.com\0"
- "From\0mathieu.poirier@linaro.org (Mathieu Poirier)\0"
- "Subject\0[PATCH V3 1/4] arm64: dts: Add basic DT to support Spreadtrum's SP9860G\0"
+ "From\0Mathieu Poirier <mathieu.poirier@linaro.org>\0"
+ "Subject\0Re: [PATCH V3 1/4] arm64: dts: Add basic DT to support Spreadtrum's SP9860G\0"
  "Date\0Thu, 2 Mar 2017 09:22:22 -0700\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
+ "To\0Chunyan Zhang <chunyan.zhang@spreadtrum.com>\0"
+ "Cc\0mark.rutland@arm.com"
+  devicetree@vger.kernel.org
+  orson.zhai@spreadtrum.com
+  arnd@arndb.de
+  gregkh@linuxfoundation.org
+  sudeep.holla@arm.com
+  will.deacon@arm.com
+  linux-kernel@vger.kernel.org
+  robh+dt@kernel.org
+  zhang.lyra@gmail.com
+  catalin.marinas@arm.com
+ " linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:\n"
@@ -92,7 +104,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU0: cpu at 530000 {\n"
+ "> +\t\tCPU0: cpu@530000 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530000>;\n"
@@ -100,7 +112,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU1: cpu at 530001 {\n"
+ "> +\t\tCPU1: cpu@530001 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530001>;\n"
@@ -108,7 +120,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU2: cpu at 530002 {\n"
+ "> +\t\tCPU2: cpu@530002 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530002>;\n"
@@ -116,7 +128,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU3: cpu at 530003 {\n"
+ "> +\t\tCPU3: cpu@530003 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530003>;\n"
@@ -124,7 +136,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU4: cpu at 530100 {\n"
+ "> +\t\tCPU4: cpu@530100 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530100>;\n"
@@ -132,7 +144,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU5: cpu at 530101 {\n"
+ "> +\t\tCPU5: cpu@530101 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530101>;\n"
@@ -140,7 +152,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU6: cpu at 530102 {\n"
+ "> +\t\tCPU6: cpu@530102 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530102>;\n"
@@ -148,7 +160,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU7: cpu at 530103 {\n"
+ "> +\t\tCPU7: cpu@530103 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530103>;\n"
@@ -179,7 +191,7 @@
  "> +\t\t};\n"
  "> +\t};\n"
  "> +\n"
- "> +\tgic: interrupt-controller at 12001000 {\n"
+ "> +\tgic: interrupt-controller@12001000 {\n"
  "> +\t\tcompatible = \"arm,gic-400\";\n"
  "> +\t\treg = <0 0x12001000 0 0x1000>,\n"
  "> +\t\t      <0 0x12002000 0 0x2000>,\n"
@@ -229,7 +241,7 @@
  "> +\t};\n"
  "> +\n"
  "> +\tsoc {\n"
- "> +\t\tfunnel at 10001000 { /* SoC Funnel */\n"
+ "> +\t\tfunnel@10001000 { /* SoC Funnel */\n"
  "> +\t\t\tcompatible = \"arm,coresight-funnel\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x10001000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
@@ -238,14 +250,14 @@
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\t\t\tport at 0 {\n"
+ "> +\t\t\t\tport@0 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tsoc_funnel_out_port: endpoint {\n"
  "> +\t\t\t\t\t\tremote-endpoint = <&etb_in>;\n"
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 1 {\n"
+ "> +\t\t\t\tport@1 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tsoc_funnel_in_port: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -256,7 +268,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetb at 10003000 {\n"
+ "> +\t\tetb@10003000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-tmc\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x10003000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
@@ -270,7 +282,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tfunnel at 11001000 { /* Cluster0 Funnel */\n"
+ "> +\t\tfunnel@11001000 { /* Cluster0 Funnel */\n"
  "> +\t\t\tcompatible = \"arm,coresight-funnel\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11001000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
@@ -279,7 +291,7 @@
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\t\t\tport at 0 {\n"
+ "> +\t\t\t\tport@0 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster0_funnel_out_port: endpoint {\n"
  "> +\t\t\t\t\t\tremote-endpoint =\n"
@@ -287,7 +299,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 1 {\n"
+ "> +\t\t\t\tport@1 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster0_funnel_in_port0: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -295,7 +307,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 2 {\n"
+ "> +\t\t\t\tport@2 {\n"
  "> +\t\t\t\t\treg = <1>;\n"
  "> +\t\t\t\t\tcluster0_funnel_in_port1: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -303,7 +315,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 3 {\n"
+ "> +\t\t\t\tport@3 {\n"
  "> +\t\t\t\t\treg = <2>;\n"
  "> +\t\t\t\t\tcluster0_funnel_in_port2: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -311,7 +323,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 4 {\n"
+ "> +\t\t\t\tport@4 {\n"
  "> +\t\t\t\t\treg = <4>;\n"
  "> +\t\t\t\t\tcluster0_funnel_in_port3: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -321,7 +333,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tfunnel at 11002000 { /* Cluster1 Funnel */\n"
+ "> +\t\tfunnel@11002000 { /* Cluster1 Funnel */\n"
  "> +\t\t\tcompatible = \"arm,coresight-funnel\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11002000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
@@ -330,7 +342,7 @@
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\t\t\tport at 0 {\n"
+ "> +\t\t\t\tport@0 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster1_funnel_out_port: endpoint {\n"
  "> +\t\t\t\t\t\tremote-endpoint =\n"
@@ -338,7 +350,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 1 {\n"
+ "> +\t\t\t\tport@1 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster1_funnel_in_port0: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -346,7 +358,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 2 {\n"
+ "> +\t\t\t\tport@2 {\n"
  "> +\t\t\t\t\treg = <1>;\n"
  "> +\t\t\t\t\tcluster1_funnel_in_port1: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -354,7 +366,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 3 {\n"
+ "> +\t\t\t\tport@3 {\n"
  "> +\t\t\t\t\treg = <2>;\n"
  "> +\t\t\t\t\tcluster1_funnel_in_port2: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -362,7 +374,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 4 {\n"
+ "> +\t\t\t\tport@4 {\n"
  "> +\t\t\t\t\treg = <3>;\n"
  "> +\t\t\t\t\tcluster1_funnel_in_port3: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -372,7 +384,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetf at 11003000 { /*  ETF on Cluster0 */\n"
+ "> +\t\tetf@11003000 { /*  ETF on Cluster0 */\n"
  "> +\t\t\tcompatible = \"arm,coresight-tmc\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11003000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
@@ -382,7 +394,7 @@
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\t\t\tport at 0 {\n"
+ "> +\t\t\t\tport@0 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster0_etf_out: endpoint {\n"
  "> +\t\t\t\t\t\tremote-endpoint =\n"
@@ -390,7 +402,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 1 {\n"
+ "> +\t\t\t\tport@1 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster0_etf_in: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -401,7 +413,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetf at 11004000 { /* ETF on Cluster1 */\n"
+ "> +\t\tetf@11004000 { /* ETF on Cluster1 */\n"
  "> +\t\t\tcompatible = \"arm,coresight-tmc\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11004000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
@@ -411,7 +423,7 @@
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\t\t\tport at 0 {\n"
+ "> +\t\t\t\tport@0 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster1_etf_out: endpoint {\n"
  "> +\t\t\t\t\t\tremote-endpoint =\n"
@@ -419,7 +431,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 1 {\n"
+ "> +\t\t\t\tport@1 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster1_etf_in: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -430,7 +442,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tfunnel at 11005000 { /* Main Funnel */\n"
+ "> +\t\tfunnel@11005000 { /* Main Funnel */\n"
  "> +\t\t\tcompatible = \"arm,coresight-funnel\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11005000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
@@ -440,7 +452,7 @@
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\t\t\tport at 0 {\n"
+ "> +\t\t\t\tport@0 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tmain_funnel_out_port: endpoint {\n"
  "> +\t\t\t\t\t\tremote-endpoint =\n"
@@ -448,7 +460,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 1 {\n"
+ "> +\t\t\t\tport@1 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tmain_funnel_in_port0: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -457,7 +469,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 2 {\n"
+ "> +\t\t\t\tport@2 {\n"
  "> +\t\t\t\t\treg = <1>;\n"
  "> +\t\t\t\t\tmain_funnel_in_port1: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -468,7 +480,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11440000 {\n"
+ "> +\t\tetm@11440000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11440000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU0>;\n"
@@ -483,7 +495,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11540000 {\n"
+ "> +\t\tetm@11540000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11540000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU1>;\n"
@@ -498,7 +510,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11640000 {\n"
+ "> +\t\tetm@11640000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11640000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU2>;\n"
@@ -513,7 +525,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11740000 {\n"
+ "> +\t\tetm@11740000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11740000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU3>;\n"
@@ -528,7 +540,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11840000 {\n"
+ "> +\t\tetm@11840000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11840000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU4>;\n"
@@ -543,7 +555,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11940000 {\n"
+ "> +\t\tetm@11940000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11940000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU5>;\n"
@@ -558,7 +570,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11a40000 {\n"
+ "> +\t\tetm@11a40000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11a40000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU6>;\n"
@@ -573,7 +585,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11b40000 {\n"
+ "> +\t\tetm@11b40000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11b40000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU7>;\n"
@@ -687,7 +699,7 @@
  "> +\t\t\t#size-cells = <1>;\n"
  "> +\t\t\tranges = <0 0x0 0x70000000 0x10000000>;\n"
  "> +\n"
- "> +\t\t\tuart0: serial at 70000000 {\n"
+ "> +\t\t\tuart0: serial@70000000 {\n"
  "> +\t\t\t\tcompatible = \"sprd,sc9860-uart\",\n"
  "> +\t\t\t\t\t     \"sprd,sc9836-uart\";\n"
  "> +\t\t\t\treg = <0x000000 0x100>;\n"
@@ -696,7 +708,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tuart1: serial at 70100000 {\n"
+ "> +\t\t\tuart1: serial@70100000 {\n"
  "> +\t\t\t\tcompatible = \"sprd,sc9860-uart\",\n"
  "> +\t\t\t\t\t     \"sprd,sc9836-uart\";\n"
  "> +\t\t\t\treg = <0x100000 0x100>;\n"
@@ -705,7 +717,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tuart2: serial at 70200000 {\n"
+ "> +\t\t\tuart2: serial@70200000 {\n"
  "> +\t\t\t\tcompatible = \"sprd,sc9860-uart\",\n"
  "> +\t\t\t\t\t     \"sprd,sc9836-uart\";\n"
  "> +\t\t\t\treg = <0x200000 0x100>;\n"
@@ -714,7 +726,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tuart3: serial at 70300000 {\n"
+ "> +\t\t\tuart3: serial@70300000 {\n"
  "> +\t\t\t\tcompatible = \"sprd,sc9860-uart\",\n"
  "> +\t\t\t\t\t     \"sprd,sc9836-uart\";\n"
  "> +\t\t\t\treg = <0x300000 0x100>;\n"
@@ -739,7 +751,7 @@
  "> \n"
  "> _______________________________________________\n"
  "> linux-arm-kernel mailing list\n"
- "> linux-arm-kernel at lists.infradead.org\n"
+ "> linux-arm-kernel@lists.infradead.org\n"
  > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
 
-3826bcac9d2cc11aeb102ca7b814d31ccb4b690428f110c6cee50d0e3e5971c0
+f660b7e9b1cd9e05ff8c0875c7c4248626b47393e4cbedbfac048d7325f8e660

diff --git a/a/1.txt b/N2/1.txt
index 1734f94..e0eb4c5 100644
--- a/a/1.txt
+++ b/N2/1.txt
@@ -84,7 +84,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		CPU0: cpu at 530000 {
+> +		CPU0: cpu@530000 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530000>;
@@ -92,7 +92,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU1: cpu at 530001 {
+> +		CPU1: cpu@530001 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530001>;
@@ -100,7 +100,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU2: cpu at 530002 {
+> +		CPU2: cpu@530002 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530002>;
@@ -108,7 +108,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU3: cpu at 530003 {
+> +		CPU3: cpu@530003 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530003>;
@@ -116,7 +116,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU4: cpu at 530100 {
+> +		CPU4: cpu@530100 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530100>;
@@ -124,7 +124,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU5: cpu at 530101 {
+> +		CPU5: cpu@530101 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530101>;
@@ -132,7 +132,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU6: cpu at 530102 {
+> +		CPU6: cpu@530102 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530102>;
@@ -140,7 +140,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
 > +		};
 > +
-> +		CPU7: cpu at 530103 {
+> +		CPU7: cpu@530103 {
 > +			device_type = "cpu";
 > +			compatible = "arm,cortex-a53", "arm,armv8";
 > +			reg = <0x0 0x530103>;
@@ -171,7 +171,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +		};
 > +	};
 > +
-> +	gic: interrupt-controller at 12001000 {
+> +	gic: interrupt-controller@12001000 {
 > +		compatible = "arm,gic-400";
 > +		reg = <0 0x12001000 0 0x1000>,
 > +		      <0 0x12002000 0 0x2000>,
@@ -221,7 +221,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +	};
 > +
 > +	soc {
-> +		funnel at 10001000 { /* SoC Funnel */
+> +		funnel@10001000 { /* SoC Funnel */
 > +			compatible = "arm,coresight-funnel", "arm,primecell";
 > +			reg = <0 0x10001000 0 0x1000>;
 > +			clocks = <&ext_26m>;
@@ -230,14 +230,14 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +
-> +				port at 0 {
+> +				port@0 {
 > +					reg = <0>;
 > +					soc_funnel_out_port: endpoint {
 > +						remote-endpoint = <&etb_in>;
 > +					};
 > +				};
 > +
-> +				port at 1 {
+> +				port@1 {
 > +					reg = <0>;
 > +					soc_funnel_in_port: endpoint {
 > +						slave-mode;
@@ -248,7 +248,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etb at 10003000 {
+> +		etb@10003000 {
 > +			compatible = "arm,coresight-tmc", "arm,primecell";
 > +			reg = <0 0x10003000 0 0x1000>;
 > +			clocks = <&ext_26m>;
@@ -262,7 +262,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		funnel at 11001000 { /* Cluster0 Funnel */
+> +		funnel@11001000 { /* Cluster0 Funnel */
 > +			compatible = "arm,coresight-funnel", "arm,primecell";
 > +			reg = <0 0x11001000 0 0x1000>;
 > +			clocks = <&ext_26m>;
@@ -271,7 +271,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +
-> +				port at 0 {
+> +				port@0 {
 > +					reg = <0>;
 > +					cluster0_funnel_out_port: endpoint {
 > +						remote-endpoint =
@@ -279,7 +279,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 1 {
+> +				port@1 {
 > +					reg = <0>;
 > +					cluster0_funnel_in_port0: endpoint {
 > +						slave-mode;
@@ -287,7 +287,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 2 {
+> +				port@2 {
 > +					reg = <1>;
 > +					cluster0_funnel_in_port1: endpoint {
 > +						slave-mode;
@@ -295,7 +295,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 3 {
+> +				port@3 {
 > +					reg = <2>;
 > +					cluster0_funnel_in_port2: endpoint {
 > +						slave-mode;
@@ -303,7 +303,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 4 {
+> +				port@4 {
 > +					reg = <4>;
 > +					cluster0_funnel_in_port3: endpoint {
 > +						slave-mode;
@@ -313,7 +313,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		funnel at 11002000 { /* Cluster1 Funnel */
+> +		funnel@11002000 { /* Cluster1 Funnel */
 > +			compatible = "arm,coresight-funnel", "arm,primecell";
 > +			reg = <0 0x11002000 0 0x1000>;
 > +			clocks = <&ext_26m>;
@@ -322,7 +322,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +
-> +				port at 0 {
+> +				port@0 {
 > +					reg = <0>;
 > +					cluster1_funnel_out_port: endpoint {
 > +						remote-endpoint =
@@ -330,7 +330,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 1 {
+> +				port@1 {
 > +					reg = <0>;
 > +					cluster1_funnel_in_port0: endpoint {
 > +						slave-mode;
@@ -338,7 +338,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 2 {
+> +				port@2 {
 > +					reg = <1>;
 > +					cluster1_funnel_in_port1: endpoint {
 > +						slave-mode;
@@ -346,7 +346,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 3 {
+> +				port@3 {
 > +					reg = <2>;
 > +					cluster1_funnel_in_port2: endpoint {
 > +						slave-mode;
@@ -354,7 +354,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 4 {
+> +				port@4 {
 > +					reg = <3>;
 > +					cluster1_funnel_in_port3: endpoint {
 > +						slave-mode;
@@ -364,7 +364,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etf at 11003000 { /*  ETF on Cluster0 */
+> +		etf@11003000 { /*  ETF on Cluster0 */
 > +			compatible = "arm,coresight-tmc", "arm,primecell";
 > +			reg = <0 0x11003000 0 0x1000>;
 > +			clocks = <&ext_26m>;
@@ -374,7 +374,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +
-> +				port at 0 {
+> +				port@0 {
 > +					reg = <0>;
 > +					cluster0_etf_out: endpoint {
 > +						remote-endpoint =
@@ -382,7 +382,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 1 {
+> +				port@1 {
 > +					reg = <0>;
 > +					cluster0_etf_in: endpoint {
 > +						slave-mode;
@@ -393,7 +393,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etf at 11004000 { /* ETF on Cluster1 */
+> +		etf@11004000 { /* ETF on Cluster1 */
 > +			compatible = "arm,coresight-tmc", "arm,primecell";
 > +			reg = <0 0x11004000 0 0x1000>;
 > +			clocks = <&ext_26m>;
@@ -403,7 +403,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +
-> +				port at 0 {
+> +				port@0 {
 > +					reg = <0>;
 > +					cluster1_etf_out: endpoint {
 > +						remote-endpoint =
@@ -411,7 +411,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 1 {
+> +				port@1 {
 > +					reg = <0>;
 > +					cluster1_etf_in: endpoint {
 > +						slave-mode;
@@ -422,7 +422,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		funnel at 11005000 { /* Main Funnel */
+> +		funnel@11005000 { /* Main Funnel */
 > +			compatible = "arm,coresight-funnel", "arm,primecell";
 > +			reg = <0 0x11005000 0 0x1000>;
 > +			clocks = <&ext_26m>;
@@ -432,7 +432,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +
-> +				port at 0 {
+> +				port@0 {
 > +					reg = <0>;
 > +					main_funnel_out_port: endpoint {
 > +						remote-endpoint =
@@ -440,7 +440,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 1 {
+> +				port@1 {
 > +					reg = <0>;
 > +					main_funnel_in_port0: endpoint {
 > +						slave-mode;
@@ -449,7 +449,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +					};
 > +				};
 > +
-> +				port at 2 {
+> +				port@2 {
 > +					reg = <1>;
 > +					main_funnel_in_port1: endpoint {
 > +						slave-mode;
@@ -460,7 +460,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etm at 11440000 {
+> +		etm@11440000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11440000 0 0x1000>;
 > +			cpu = <&CPU0>;
@@ -475,7 +475,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etm at 11540000 {
+> +		etm@11540000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11540000 0 0x1000>;
 > +			cpu = <&CPU1>;
@@ -490,7 +490,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etm at 11640000 {
+> +		etm@11640000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11640000 0 0x1000>;
 > +			cpu = <&CPU2>;
@@ -505,7 +505,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etm at 11740000 {
+> +		etm@11740000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11740000 0 0x1000>;
 > +			cpu = <&CPU3>;
@@ -520,7 +520,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etm at 11840000 {
+> +		etm@11840000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11840000 0 0x1000>;
 > +			cpu = <&CPU4>;
@@ -535,7 +535,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etm at 11940000 {
+> +		etm@11940000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11940000 0 0x1000>;
 > +			cpu = <&CPU5>;
@@ -550,7 +550,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etm at 11a40000 {
+> +		etm@11a40000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11a40000 0 0x1000>;
 > +			cpu = <&CPU6>;
@@ -565,7 +565,7 @@ On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:
 > +			};
 > +		};
 > +
-> +		etm at 11b40000 {
+> +		etm@11b40000 {
 > +			compatible = "arm,coresight-etm4x", "arm,primecell";
 > +			reg = <0 0x11b40000 0 0x1000>;
 > +			cpu = <&CPU7>;
@@ -679,7 +679,7 @@ Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
 > +			#size-cells = <1>;
 > +			ranges = <0 0x0 0x70000000 0x10000000>;
 > +
-> +			uart0: serial at 70000000 {
+> +			uart0: serial@70000000 {
 > +				compatible = "sprd,sc9860-uart",
 > +					     "sprd,sc9836-uart";
 > +				reg = <0x000000 0x100>;
@@ -688,7 +688,7 @@ Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
 > +				status = "disabled";
 > +			};
 > +
-> +			uart1: serial at 70100000 {
+> +			uart1: serial@70100000 {
 > +				compatible = "sprd,sc9860-uart",
 > +					     "sprd,sc9836-uart";
 > +				reg = <0x100000 0x100>;
@@ -697,7 +697,7 @@ Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
 > +				status = "disabled";
 > +			};
 > +
-> +			uart2: serial at 70200000 {
+> +			uart2: serial@70200000 {
 > +				compatible = "sprd,sc9860-uart",
 > +					     "sprd,sc9836-uart";
 > +				reg = <0x200000 0x100>;
@@ -706,7 +706,7 @@ Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
 > +				status = "disabled";
 > +			};
 > +
-> +			uart3: serial at 70300000 {
+> +			uart3: serial@70300000 {
 > +				compatible = "sprd,sc9860-uart",
 > +					     "sprd,sc9836-uart";
 > +				reg = <0x300000 0x100>;
@@ -731,5 +731,5 @@ Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
 > 
 > _______________________________________________
 > linux-arm-kernel mailing list
-> linux-arm-kernel at lists.infradead.org
+> linux-arm-kernel@lists.infradead.org
 > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff --git a/a/content_digest b/N2/content_digest
index 4728e2b..a0e8d4c 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -1,9 +1,21 @@
  "ref\01488435730-6711-1-git-send-email-chunyan.zhang@spreadtrum.com\0"
  "ref\01488435730-6711-2-git-send-email-chunyan.zhang@spreadtrum.com\0"
- "From\0mathieu.poirier@linaro.org (Mathieu Poirier)\0"
- "Subject\0[PATCH V3 1/4] arm64: dts: Add basic DT to support Spreadtrum's SP9860G\0"
+ "From\0Mathieu Poirier <mathieu.poirier@linaro.org>\0"
+ "Subject\0Re: [PATCH V3 1/4] arm64: dts: Add basic DT to support Spreadtrum's SP9860G\0"
  "Date\0Thu, 2 Mar 2017 09:22:22 -0700\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
+ "To\0Chunyan Zhang <chunyan.zhang@spreadtrum.com>\0"
+ "Cc\0robh+dt@kernel.org"
+  mark.rutland@arm.com
+  gregkh@linuxfoundation.org
+  catalin.marinas@arm.com
+  will.deacon@arm.com
+  arnd@arndb.de
+  devicetree@vger.kernel.org
+  orson.zhai@spreadtrum.com
+  zhang.lyra@gmail.com
+  linux-kernel@vger.kernel.org
+  sudeep.holla@arm.com
+ " linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "On Thu, Mar 02, 2017 at 02:22:07PM +0800, Chunyan Zhang wrote:\n"
@@ -92,7 +104,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU0: cpu at 530000 {\n"
+ "> +\t\tCPU0: cpu@530000 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530000>;\n"
@@ -100,7 +112,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU1: cpu at 530001 {\n"
+ "> +\t\tCPU1: cpu@530001 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530001>;\n"
@@ -108,7 +120,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU2: cpu at 530002 {\n"
+ "> +\t\tCPU2: cpu@530002 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530002>;\n"
@@ -116,7 +128,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU3: cpu at 530003 {\n"
+ "> +\t\tCPU3: cpu@530003 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530003>;\n"
@@ -124,7 +136,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU4: cpu at 530100 {\n"
+ "> +\t\tCPU4: cpu@530100 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530100>;\n"
@@ -132,7 +144,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU5: cpu at 530101 {\n"
+ "> +\t\tCPU5: cpu@530101 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530101>;\n"
@@ -140,7 +152,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU6: cpu at 530102 {\n"
+ "> +\t\tCPU6: cpu@530102 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530102>;\n"
@@ -148,7 +160,7 @@
  "> +\t\t\tcpu-idle-states = <&CORE_PD &CLUSTER_PD>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU7: cpu at 530103 {\n"
+ "> +\t\tCPU7: cpu@530103 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n"
  "> +\t\t\treg = <0x0 0x530103>;\n"
@@ -179,7 +191,7 @@
  "> +\t\t};\n"
  "> +\t};\n"
  "> +\n"
- "> +\tgic: interrupt-controller at 12001000 {\n"
+ "> +\tgic: interrupt-controller@12001000 {\n"
  "> +\t\tcompatible = \"arm,gic-400\";\n"
  "> +\t\treg = <0 0x12001000 0 0x1000>,\n"
  "> +\t\t      <0 0x12002000 0 0x2000>,\n"
@@ -229,7 +241,7 @@
  "> +\t};\n"
  "> +\n"
  "> +\tsoc {\n"
- "> +\t\tfunnel at 10001000 { /* SoC Funnel */\n"
+ "> +\t\tfunnel@10001000 { /* SoC Funnel */\n"
  "> +\t\t\tcompatible = \"arm,coresight-funnel\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x10001000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
@@ -238,14 +250,14 @@
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\t\t\tport at 0 {\n"
+ "> +\t\t\t\tport@0 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tsoc_funnel_out_port: endpoint {\n"
  "> +\t\t\t\t\t\tremote-endpoint = <&etb_in>;\n"
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 1 {\n"
+ "> +\t\t\t\tport@1 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tsoc_funnel_in_port: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -256,7 +268,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetb at 10003000 {\n"
+ "> +\t\tetb@10003000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-tmc\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x10003000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
@@ -270,7 +282,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tfunnel at 11001000 { /* Cluster0 Funnel */\n"
+ "> +\t\tfunnel@11001000 { /* Cluster0 Funnel */\n"
  "> +\t\t\tcompatible = \"arm,coresight-funnel\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11001000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
@@ -279,7 +291,7 @@
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\t\t\tport at 0 {\n"
+ "> +\t\t\t\tport@0 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster0_funnel_out_port: endpoint {\n"
  "> +\t\t\t\t\t\tremote-endpoint =\n"
@@ -287,7 +299,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 1 {\n"
+ "> +\t\t\t\tport@1 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster0_funnel_in_port0: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -295,7 +307,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 2 {\n"
+ "> +\t\t\t\tport@2 {\n"
  "> +\t\t\t\t\treg = <1>;\n"
  "> +\t\t\t\t\tcluster0_funnel_in_port1: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -303,7 +315,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 3 {\n"
+ "> +\t\t\t\tport@3 {\n"
  "> +\t\t\t\t\treg = <2>;\n"
  "> +\t\t\t\t\tcluster0_funnel_in_port2: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -311,7 +323,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 4 {\n"
+ "> +\t\t\t\tport@4 {\n"
  "> +\t\t\t\t\treg = <4>;\n"
  "> +\t\t\t\t\tcluster0_funnel_in_port3: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -321,7 +333,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tfunnel at 11002000 { /* Cluster1 Funnel */\n"
+ "> +\t\tfunnel@11002000 { /* Cluster1 Funnel */\n"
  "> +\t\t\tcompatible = \"arm,coresight-funnel\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11002000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
@@ -330,7 +342,7 @@
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\t\t\tport at 0 {\n"
+ "> +\t\t\t\tport@0 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster1_funnel_out_port: endpoint {\n"
  "> +\t\t\t\t\t\tremote-endpoint =\n"
@@ -338,7 +350,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 1 {\n"
+ "> +\t\t\t\tport@1 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster1_funnel_in_port0: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -346,7 +358,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 2 {\n"
+ "> +\t\t\t\tport@2 {\n"
  "> +\t\t\t\t\treg = <1>;\n"
  "> +\t\t\t\t\tcluster1_funnel_in_port1: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -354,7 +366,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 3 {\n"
+ "> +\t\t\t\tport@3 {\n"
  "> +\t\t\t\t\treg = <2>;\n"
  "> +\t\t\t\t\tcluster1_funnel_in_port2: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -362,7 +374,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 4 {\n"
+ "> +\t\t\t\tport@4 {\n"
  "> +\t\t\t\t\treg = <3>;\n"
  "> +\t\t\t\t\tcluster1_funnel_in_port3: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -372,7 +384,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetf at 11003000 { /*  ETF on Cluster0 */\n"
+ "> +\t\tetf@11003000 { /*  ETF on Cluster0 */\n"
  "> +\t\t\tcompatible = \"arm,coresight-tmc\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11003000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
@@ -382,7 +394,7 @@
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\t\t\tport at 0 {\n"
+ "> +\t\t\t\tport@0 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster0_etf_out: endpoint {\n"
  "> +\t\t\t\t\t\tremote-endpoint =\n"
@@ -390,7 +402,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 1 {\n"
+ "> +\t\t\t\tport@1 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster0_etf_in: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -401,7 +413,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetf at 11004000 { /* ETF on Cluster1 */\n"
+ "> +\t\tetf@11004000 { /* ETF on Cluster1 */\n"
  "> +\t\t\tcompatible = \"arm,coresight-tmc\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11004000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
@@ -411,7 +423,7 @@
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\t\t\tport at 0 {\n"
+ "> +\t\t\t\tport@0 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster1_etf_out: endpoint {\n"
  "> +\t\t\t\t\t\tremote-endpoint =\n"
@@ -419,7 +431,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 1 {\n"
+ "> +\t\t\t\tport@1 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tcluster1_etf_in: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -430,7 +442,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tfunnel at 11005000 { /* Main Funnel */\n"
+ "> +\t\tfunnel@11005000 { /* Main Funnel */\n"
  "> +\t\t\tcompatible = \"arm,coresight-funnel\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11005000 0 0x1000>;\n"
  "> +\t\t\tclocks = <&ext_26m>;\n"
@@ -440,7 +452,7 @@
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\t\t\tport at 0 {\n"
+ "> +\t\t\t\tport@0 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tmain_funnel_out_port: endpoint {\n"
  "> +\t\t\t\t\t\tremote-endpoint =\n"
@@ -448,7 +460,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 1 {\n"
+ "> +\t\t\t\tport@1 {\n"
  "> +\t\t\t\t\treg = <0>;\n"
  "> +\t\t\t\t\tmain_funnel_in_port0: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -457,7 +469,7 @@
  "> +\t\t\t\t\t};\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tport at 2 {\n"
+ "> +\t\t\t\tport@2 {\n"
  "> +\t\t\t\t\treg = <1>;\n"
  "> +\t\t\t\t\tmain_funnel_in_port1: endpoint {\n"
  "> +\t\t\t\t\t\tslave-mode;\n"
@@ -468,7 +480,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11440000 {\n"
+ "> +\t\tetm@11440000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11440000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU0>;\n"
@@ -483,7 +495,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11540000 {\n"
+ "> +\t\tetm@11540000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11540000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU1>;\n"
@@ -498,7 +510,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11640000 {\n"
+ "> +\t\tetm@11640000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11640000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU2>;\n"
@@ -513,7 +525,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11740000 {\n"
+ "> +\t\tetm@11740000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11740000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU3>;\n"
@@ -528,7 +540,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11840000 {\n"
+ "> +\t\tetm@11840000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11840000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU4>;\n"
@@ -543,7 +555,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11940000 {\n"
+ "> +\t\tetm@11940000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11940000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU5>;\n"
@@ -558,7 +570,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11a40000 {\n"
+ "> +\t\tetm@11a40000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11a40000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU6>;\n"
@@ -573,7 +585,7 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tetm at 11b40000 {\n"
+ "> +\t\tetm@11b40000 {\n"
  "> +\t\t\tcompatible = \"arm,coresight-etm4x\", \"arm,primecell\";\n"
  "> +\t\t\treg = <0 0x11b40000 0 0x1000>;\n"
  "> +\t\t\tcpu = <&CPU7>;\n"
@@ -687,7 +699,7 @@
  "> +\t\t\t#size-cells = <1>;\n"
  "> +\t\t\tranges = <0 0x0 0x70000000 0x10000000>;\n"
  "> +\n"
- "> +\t\t\tuart0: serial at 70000000 {\n"
+ "> +\t\t\tuart0: serial@70000000 {\n"
  "> +\t\t\t\tcompatible = \"sprd,sc9860-uart\",\n"
  "> +\t\t\t\t\t     \"sprd,sc9836-uart\";\n"
  "> +\t\t\t\treg = <0x000000 0x100>;\n"
@@ -696,7 +708,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tuart1: serial at 70100000 {\n"
+ "> +\t\t\tuart1: serial@70100000 {\n"
  "> +\t\t\t\tcompatible = \"sprd,sc9860-uart\",\n"
  "> +\t\t\t\t\t     \"sprd,sc9836-uart\";\n"
  "> +\t\t\t\treg = <0x100000 0x100>;\n"
@@ -705,7 +717,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tuart2: serial at 70200000 {\n"
+ "> +\t\t\tuart2: serial@70200000 {\n"
  "> +\t\t\t\tcompatible = \"sprd,sc9860-uart\",\n"
  "> +\t\t\t\t\t     \"sprd,sc9836-uart\";\n"
  "> +\t\t\t\treg = <0x200000 0x100>;\n"
@@ -714,7 +726,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tuart3: serial at 70300000 {\n"
+ "> +\t\t\tuart3: serial@70300000 {\n"
  "> +\t\t\t\tcompatible = \"sprd,sc9860-uart\",\n"
  "> +\t\t\t\t\t     \"sprd,sc9836-uart\";\n"
  "> +\t\t\t\treg = <0x300000 0x100>;\n"
@@ -739,7 +751,7 @@
  "> \n"
  "> _______________________________________________\n"
  "> linux-arm-kernel mailing list\n"
- "> linux-arm-kernel at lists.infradead.org\n"
+ "> linux-arm-kernel@lists.infradead.org\n"
  > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
 
-3826bcac9d2cc11aeb102ca7b814d31ccb4b690428f110c6cee50d0e3e5971c0
+165e72e2c172687f244d802a4d057ee41b23fe3691fc0c8504ee94e44769c08f

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