From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: Extend residency counter ranges on chv and byt Date: Thu, 2 Mar 2017 20:13:31 +0200 Message-ID: <20170302181331.GI31595@intel.com> References: <1488477700-30550-1-git-send-email-mika.kuoppala@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 637AF6EC0E for ; Thu, 2 Mar 2017 18:13:38 +0000 (UTC) Content-Disposition: inline In-Reply-To: <1488477700-30550-1-git-send-email-mika.kuoppala@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Mika Kuoppala Cc: Len Brown , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org T24gVGh1LCBNYXIgMDIsIDIwMTcgYXQgMDg6MDE6NDBQTSArMDIwMCwgTWlrYSBLdW9wcGFsYSB3 cm90ZToKPiBXZSB3ZXJlIHBhc3NpdmVseSBhY3Rpbmcgb24gdGhlIGhpZ2ggY291bnRlciB2YWx1 ZSBiaXQKPiBhbmQgYXMgaXQgd2FzIG5ldmVyIHNldCwgd2Ugd2VyZSBvbmx5IHV0aWxpemluZyB0 aGUKPiB0aGUgMzJiaXRzIG9mIHJlc29sdXRpb24uIEFzIHRoZSBkaXZpc29yIHdpdGggdGhlc2Ug cGxhdGZvcm1zCj4gaXMgcXVpdGUgaGlnaCwgdGhlIHdyYXAgYXJvdW5kIGhhcHBlbmVkIGluIHRo ZSBsZXNzIHRoYW4gMTMgc2Vjb25kcy4KPiAKPiBJZiB3ZSB0b2dnbGUgdGhlIHJlc29sdXRpb24g Yml0IGluIHRoZSBjb250cm9sIHJlZ2lzdGVyIGFuZAoKQ2FuJ3QgYmUgZG9uZSBvbiBhbGwgbWFj aGluZXMuIElJUkMgYm90aCBDaHJpcyBhbmQgbWUgdHJpZWQgdGhpcyBhdApzb21lIHBvaW50IGFu ZCBvbiBzb21lIG1hY2hpbmVzIHRoZSByZWdpc3RlciB3YXMgbG9ja2VkLiBBbHNvIEknbQpub3Qg c3VyZSBpZiBzb21lIHBpZWNlIG9mIGZpcm13YXJlIGRlcGVuZHMgb24gdGhlIG9yaWdpbmFsIHNl dHRpbmcuCgo+IHJlYWQgdHdpY2Ugd2UgY2FuIGdldCA4IGJpdHMgbW9yZSwgYnJpbmdpbmcgdGhl IHdyYXAgaW4KPiA1NCBtaW51dGUgcmFuZ2UuCj4gCj4gUmVwb3J0ZWQtYnk6IExlbiBCcm93biA8 bGVuLmJyb3duQGludGVsLmNvbT4KPiBDYzogQ2hyaXMgV2lsc29uIDxjaHJpc0BjaHJpcy13aWxz b24uY28udWs+Cj4gQ2M6IFZpbGxlIFN5cmrDpGzDpCA8dmlsbGUuc3lyamFsYUBsaW51eC5pbnRl bC5jb20+Cj4gQ2M6IExlbiBCcm93biA8bGVuLmJyb3duQGludGVsLmNvbT4KPiBTaWduZWQtb2Zm LWJ5OiBNaWthIEt1b3BwYWxhIDxtaWthLmt1b3BwYWxhQGludGVsLmNvbT4KPiAtLS0KPiAgZHJp dmVycy9ncHUvZHJtL2k5MTUvaTkxNV9zeXNmcy5jIHwgMTUgKysrKysrKysrKysrLS0tCj4gIDEg ZmlsZSBjaGFuZ2VkLCAxMiBpbnNlcnRpb25zKCspLCAzIGRlbGV0aW9ucygtKQo+IAo+IGRpZmYg LS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1X3N5c2ZzLmMgYi9kcml2ZXJzL2dwdS9k cm0vaTkxNS9pOTE1X3N5c2ZzLmMKPiBpbmRleCBhZjBhYzlmLi44MDdkN2JlIDEwMDY0NAo+IC0t LSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfc3lzZnMuYwo+ICsrKyBiL2RyaXZlcnMvZ3B1 L2RybS9pOTE1L2k5MTVfc3lzZnMuYwo+IEBAIC01MywxNyArNTMsMjYgQEAgc3RhdGljIHUzMiBj YWxjX3Jlc2lkZW5jeShzdHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqZGV2X3ByaXYsCj4gIAo+ICAJ LyogT24gVkxWIGFuZCBDSFYsIHJlc2lkZW5jeSB0aW1lIGlzIGluIENaIHVuaXRzIHJhdGhlciB0 aGFuIDEuMjh1cyAqLwo+ICAJaWYgKElTX1ZBTExFWVZJRVcoZGV2X3ByaXYpIHx8IElTX0NIRVJS WVZJRVcoZGV2X3ByaXYpKSB7Cj4gLQkJdW5pdHMgPSAxOwo+ICsJCXUzMiBsb3dlciwgdXBwZXI7 Cj4gIAkJZGl2ID0gZGV2X3ByaXYtPmN6Y2xrX2ZyZXE7Cj4gIAo+IC0JCWlmIChJOTE1X1JFQUQo VkxWX0NPVU5URVJfQ09OVFJPTCkgJiBWTFZfQ09VTlRfUkFOR0VfSElHSCkKPiAtCQkJdW5pdHMg PDw9IDg7Cj4gKwkJSTkxNV9XUklURShWTFZfQ09VTlRFUl9DT05UUk9MLAo+ICsJCQkgICBfTUFT S0VEX0JJVF9FTkFCTEUoVkxWX0NPVU5UX1JBTkdFX0hJR0gpKTsKPiArCQl1cHBlciA9IEk5MTVf UkVBRChyZWcpOwo+ICsKPiArCQlJOTE1X1dSSVRFKFZMVl9DT1VOVEVSX0NPTlRST0wsCj4gKwkJ CSAgIF9NQVNLRURfQklUX0RJU0FCTEUoVkxWX0NPVU5UX1JBTkdFX0hJR0gpKTsKPiArCQlsb3dl ciA9IEk5MTVfUkVBRChyZWcpOwo+ICsKPiArCQlyYXdfdGltZSA9IGxvd2VyIHwgKHU2NCl1cHBl ciA8PCA4Owo+ICsJCWdvdG8gb3V0Owo+ICAJfSBlbHNlIGlmIChJU19HRU45X0xQKGRldl9wcml2 KSkgewo+ICAJCXVuaXRzID0gMTsKPiAgCQlkaXYgPSAxMjAwOwkJLyogODMzLjMzbnMgKi8KPiAg CX0KPiAgCj4gIAlyYXdfdGltZSA9IEk5MTVfUkVBRChyZWcpICogdW5pdHM7Cj4gKyBvdXQ6Cj4g IAlyZXQgPSBESVZfUk9VTkRfVVBfVUxMKHJhd190aW1lLCBkaXYpOwo+ICAKPiAgCWludGVsX3J1 bnRpbWVfcG1fcHV0KGRldl9wcml2KTsKPiAtLSAKPiAyLjcuNAoKLS0gClZpbGxlIFN5cmrDpGzD pApJbnRlbCBPVEMKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3Jn Cmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4 Cg==