From: Segher Boessenkool <segher@kernel.crashing.org>
To: Michael Ellerman <mpe@ellerman.id.au>
Cc: pc@us.ibm.com, linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH v2] powerpc: A new cache geometry aux vectors
Date: Mon, 6 Mar 2017 02:24:06 -0600 [thread overview]
Message-ID: <20170306082405.GQ31469@gate.crashing.org> (raw)
In-Reply-To: <87r32bot2x.fsf@concordia.ellerman.id.au>
On Mon, Mar 06, 2017 at 04:46:46PM +1100, Michael Ellerman wrote:
> Hmm, which p9 mambo is this? I get:
>
> test: cache_shape
> tags: git_version:v4.10-10927-g0a55d1671c33
> L1I cache size: 0x8000 32768B 32K
> L1I line size: 0x80 128-way associative
> L1D cache size: 0x8000 32768B 32K
> L1D line size: 0x80 128-way associative
> L2 cache size: 0 0B 0K
> L2 line size: 0 fully associative
> L3 cache size: 0 0B 0K
> L3 line size: 0 fully associative
> success: cache_shape
>
> So that looks OK, other than that here is no L2/L3 info.
128 ways? Looks okay? Erm...
Segher
prev parent reply other threads:[~2017-03-06 8:24 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-02 6:22 [PATCH v2] powerpc: A new cache geometry aux vectors Benjamin Herrenschmidt
2017-03-01 20:53 ` Paul Clarke
2017-03-02 6:33 ` Michael Ellerman
2017-03-02 23:46 ` Paul Clarke
2017-03-03 4:01 ` Michael Ellerman
2017-03-03 13:51 ` Paul Clarke
2017-03-05 23:11 ` Benjamin Herrenschmidt
2017-03-06 5:46 ` Michael Ellerman
2017-03-06 8:24 ` Segher Boessenkool [this message]
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