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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org,
	"# v4 . 11-rc1+" <drm-intel-fixes@lists.freedesktop.org>
Subject: Re: [PATCH] drm/i915: Align "unfenced" tiled access on gen2, early gen3
Date: Mon, 27 Mar 2017 13:36:14 +0300	[thread overview]
Message-ID: <20170327103614.GI30290@intel.com> (raw)
In-Reply-To: <20170325113243.16438-1-chris@chris-wilson.co.uk>

On Sat, Mar 25, 2017 at 11:32:43AM +0000, Chris Wilson wrote:
> Old devices have quite severe restrictions for using fences, and unlike
> more recent device (anything from Pineview onwards) we need to enforce
> those restrictions even for unfenced tiled access from the render
> pipeline.
> 
> Fixes: 944397f04f24 ("drm/i915: Store required fence size/alignment for GGTT vma")
> Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: <drm-intel-fixes@lists.freedesktop.org> # v4.11-rc1+

Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h            | 1 +
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +++-
>  drivers/gpu/drm/i915/i915_pci.c            | 5 +++++
>  3 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2911c49113b0..86f097db8ef6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -853,6 +853,7 @@ struct intel_csr {
>  	func(has_resource_streamer); \
>  	func(has_runtime_pm); \
>  	func(has_snoop); \
> +	func(unfenced_needs_alignment); \
>  	func(cursor_needs_physical); \
>  	func(hws_needs_physical); \
>  	func(overlay_needs_physical); \
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index dd7181ed5eca..a3e59c8ef27b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -890,6 +890,7 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
>  	struct list_head ordered_vmas;
>  	struct list_head pinned_vmas;
>  	bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4;
> +	bool needs_unfenced_map = INTEL_INFO(engine->i915)->unfenced_needs_alignment;
>  	int retry;
>  
>  	vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
> @@ -910,7 +911,8 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
>  		if (!has_fenced_gpu_access)
>  			entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
>  		need_fence =
> -			entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
> +			(entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
> +			 needs_unfenced_map) &&
>  			i915_gem_object_is_tiled(obj);
>  		need_mappable = need_fence || need_reloc_mappable(vma);
>  
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 732101ed57fb..f87b0c4e564d 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -61,6 +61,7 @@
>  	.has_overlay = 1, .overlay_needs_physical = 1, \
>  	.has_gmch_display = 1, \
>  	.hws_needs_physical = 1, \
> +	.unfenced_needs_alignment = 1, \
>  	.ring_mask = RENDER_RING, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	CURSOR_OFFSETS
> @@ -102,6 +103,7 @@ static const struct intel_device_info intel_i915g_info = {
>  	.platform = INTEL_I915G, .cursor_needs_physical = 1,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
>  	.hws_needs_physical = 1,
> +	.unfenced_needs_alignment = 1,
>  };
>  
>  static const struct intel_device_info intel_i915gm_info = {
> @@ -113,6 +115,7 @@ static const struct intel_device_info intel_i915gm_info = {
>  	.supports_tv = 1,
>  	.has_fbc = 1,
>  	.hws_needs_physical = 1,
> +	.unfenced_needs_alignment = 1,
>  };
>  
>  static const struct intel_device_info intel_i945g_info = {
> @@ -121,6 +124,7 @@ static const struct intel_device_info intel_i945g_info = {
>  	.has_hotplug = 1, .cursor_needs_physical = 1,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
>  	.hws_needs_physical = 1,
> +	.unfenced_needs_alignment = 1,
>  };
>  
>  static const struct intel_device_info intel_i945gm_info = {
> @@ -131,6 +135,7 @@ static const struct intel_device_info intel_i945gm_info = {
>  	.supports_tv = 1,
>  	.has_fbc = 1,
>  	.hws_needs_physical = 1,
> +	.unfenced_needs_alignment = 1,
>  };
>  
>  static const struct intel_device_info intel_g33_info = {
> -- 
> 2.11.0

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

      parent reply	other threads:[~2017-03-27 10:36 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-25 11:32 [PATCH] drm/i915: Align "unfenced" tiled access on gen2, early gen3 Chris Wilson
2017-03-25 11:55 ` ✗ Fi.CI.BAT: failure for " Patchwork
2017-03-27 12:24   ` Chris Wilson
2017-03-27  7:10 ` [PATCH] " Daniel Vetter
2017-03-27 10:22 ` Joonas Lahtinen
2017-03-27 10:36 ` Ville Syrjälä [this message]

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